Lab 3 - EE 421L
The purpose of Lab 3 is to layout the 10-bit DAC that was designed in Lab 2.
Lab
In this lab, I created a layout of the 10-bit DAC.
The first step was to create a 10k resistor.
The dimensions of the resistor were found by using the equation below.
R = Rd * (L/W)
R = 10k ohms
Rd = 800
W = 3.6 microns
10k = 800 * (L/3.6 microns)
L = 45 microns
The dimensions I used were 45 microns and 3.6 microns.
Below is a picture of the resistor properties in Cadence.
This is a picture of the resistor.
Finally, here is an extracted view of the resistor.
Next, I took the resistor and decided to layout a single cell. The schematic of the cell is shown below.
After I made the layout for a single bit, I created the layout for the full DAC.
This was based off of the design seen below.
Below is the full layout of the 10-bit DAC.
This is my example of a single bit within my full 10-bit DAC layout.
For reference, I have displayed the other 9 bits below.
For the final step, I needed to check whether my DAC layout was DRC and LVS clean.
The LVS check can be seen below.
Here is my DRC check.
With my design passing the DRC and LVS check, my 10-bit DAC layout is complete.
Click here to download the lab3 zip files.