Lab 6 - EE 421L
October 6, 2021
Lab Purpose
The purpose of this lab is to design, layout, and simulate a CMOS NAND Gate, XOR Gate, and Full-Adder.
Prelab
For the prelab, I went through tutorial 4 which outlines the creation of a CMOS NAND Gate.
Below are the results of that effort.
Schematic
Symbol
Layout
Extracted
LVS and DRC
In order to ensure that the netlist passed, the pmos needed to be changed from 12u/0.6u to 6u/0.6u.
To check whether the CMOS values are correct, the following settings must be applied.
Go to NCSU -> Modify LVS rules. Then click check the following boxes.
Testing Schematic
Simulation Graph
The graph above proves that the NAND gate is working. Whenever both inputs are high, the output should be 0. At any other instance, the output should be 1.
Lab
NAND Gate
Schematic
Symbol
Layout
Extracted
LVS and DRC
After creating the NAND gate, I tested it by utilizing the circuit seen below.
Simulation Schematic
Simulation Graph
The simulation graph shows that the NAND gate is working properly since the NAND gate matches the truth table shown below.
| A | B | Out |
| 0 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
In the simulation graph, there are definitely glitches in the output. This is because inputs A and B temporarily both surpass the Voltage threshold for the gain on the MOSFETS.
This means that the circuit perceives this temporary instance as two inputs of 1. Therefore, the output dips and then recovers after the input stabilizes.
XOR Gate
Schematic
Symbol
Layout
Extracted
LVS and DRC
After creating the XOR gate, I tested it by utilizing the circuit seen below.
Simulation Schematic
Simulation Graph
The simulation graph shows that the XOR gate is working properly since the XOR gate matches the truth table displayed below.
| A | B | Out |
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Once again, there are definitely glitches in the output since the circuit temporarily perceives the two inputs as a logical 1 at the rising/falling edges.
Full Adder
For the final part of the lab, a full adder will be created by using the NAND gates and XOR gates previously created in parts 1 and 2 of the lab.
A full adder basically adds bits together that are of the same significance. This means that they are weighted the same.
There are two outputs of a full adder which include cout and sum. Cout is considered the most significant bit in this small scale adder and sum is considered the least significant bit.
Schematic
Symbol
Layout
Extracted
LVS and DRC
After finally finishing the layout of the full adder, I decided to test its functionality by creating a simulation circuit with the full adder.
Below are the results.
Simulation Schematic
Simulation Graph
The simulation graph shows that the full adder is working properly since the full adder matches the truth table displayed below.
| a | b | cin | cout | s |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 |
| 0 | 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 0 |
| 1 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 |