Lab 8
EE 421L 

Authored by Kaione Daniels, Jimmy Ruangnol, Ricardo Rodriguez

Email: daniek8@unlv.nevada.edu, ruangnol@unlv.nevada.edu, rodrir15@unlv.nevada.edu

November 10, 2021

  

Lab Contributions:

 

Kaione Daniels: 

 

Full Adder

10 Bit0DAC

25KΩ N-Well Resistor

Implemented all parts to the chip

Assisted with the drafting of the lab report.

 

Jimmy Ruangnol: 

 

31-stage ring oscillator to drive 20pF load

Voltage Divider

Assisted with the drafting of the lab report.

 

Ricardo Rodriguez: 

 

NAND and NOR gates

Inverter

PMOS and NMOS transistors

Assisted with the drafting of the lab report.

 

Lab Description:

 
This lab will go over the generation of a test chip that is composed of several circuits and components that are implemented in a 40-pin pad frame. The team is composed of Kaione, Jimmy, and Ricardo. 

Prelab:

 
We will be using Cadence Tutorial 6 to complete the circuit layout of the 40 pin padframe. The 40 pin padframe will consist of 40 75µm x 75µm pads. The pad consists of a layer of metal3 with a layer of overglass marked above.
 
The photo below is a layout of a single 75µm x 75µm pad.

 
The photo below is a layout of the 40-pin padframe.

 
Lab
 
For this portion of the lab, various of components from past labs are taken and added onto the 40-pin padframe to create a test chip that accurately measures circuit operations.
 
The component list for the test structures:
    • 10 Bit-DAC
     • Full Adder
    • 31-stage ring oscillator to drive 20pF load
    • NAND and NOR gates
    • Inverter
    • PMOS and NMOS transistors
    • 25KΩ N-Well Resistor
    • Voltage Divider
 
Chip Pin #Pin DescriptionComments
1AFull Adder Input
2BFull Adder Input
3CinFull Adder Input
4CoutFull Adder Output
5SFull Adder Output
 
Chip Pin #Pin DescriptionComments
6osc_out31-Ring Ocsillator
 
Chip Pin #Pin DescriptionComments
7ANAND Input
8BNAND Input
9AnandBNAND Output
10ANOR Input
11BNOR Input
12AnorBNOR Output
13AInverter Input
14AiInverter Output
 
Chip Pin #Pin DescriptionComments
15GPMOS Gate
16SPMOS Source
17DPMOS Drain
18BPMOS Body
19GNMOS Gate
20GNDGROUND
21SNMOS Source
22DNMOS Drain

Chip Pin #Pin DescriptionComments
2310KVoltage Divider Input
2425KVoltage Divider Input
25OutVoltage Divider Output
 
Chip Pin #Pin DescriptionComments
26B010-Bit DAC Input
27B110-Bit DAC Input
28B210-Bit DAC Input
29B310-Bit DAC Input
30B410-Bit DAC Input
31B510-Bit DAC Input
32B610-Bit DAC Input
33B710-Bit DAC Input
34B810-Bit DAC Input
35B910-Bit DAC Input
36Vout10-Bit DAC Output
 
Chip Pin #Pin DescriptionComments
37AXOR Input
38BXOR Input
39AxorBXOR Output
40VDD!VDD!
 
Schematic:
 
The photo below is the schematic of our test structures used for the 40-pin padframe and the pin connections.
 

 
The photo below is the layout and extracted version of the test structures.
 
 
The photos below are the schematic check, DRC, LVS, and net-list check of the Test Chip.
 



 
Layout Details:
 

 
Full Adder:
 
 
31-Ring Oscilllator:
 
 
NAND Gate, NOR Gate, and INVERTER:
 

 
NAND LAYOUTNAND EXTRACTED
NOR LAYOUTNOR EXTRACTED
INVERTER LAYOUTINVERTER LAYOUT
 
PMOS and NMOS Transistors:
 

 
PMOS LAYOUTPMOS EXTRACTED
NMOS LAYOUTNMOS EXTRACTED

Voltage Divider, 10-Bit DAC, and XOR Gate

 
Voltage Divider Layout and Extracted:
 
 
10-Bit DAC Layout and Extracted:
 

XOR Layout and Extracted: 

 

 

 

This concludes our group's lab 8 test chip design.

The files of the chip can be found here

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