lab7

Lab 7 - EE 421L

Author: Kaione Daniels

Email: daniek8@unlv.nevada.edu

October 20, 2021

Lab Purpose
The purpose of Lab 7 is to introduce buses and arrays. These buses and arrays will then be used in the design of word inverters, muxes, and adders.

Pre-lab

In the prelab, I followed tutorial 5 which went over the design and layout of a ring oscillator.

Here is the first schematic I created without the use of arrays.

Next, is the graph for the ring oscillator.

After that, I used the array functionality of cadence in order to condense the ring oscillator design.

With this new technique, the schematic looks like this.

After that, I moved onto the layout of the ring oscillator. I basically duplicated 31 inverters in a row and connected them. The finished layout is shown below.

Here is a closer view of one of the inverters with the visible pin labels.

Here's the extracted version.

Finally, I made sure that my layout was DRC and LVS clean.

With that out of the way, I finally created a symbol for the ring oscillator which is displayed below.

Here's the schematic that I used for testing the symbol.

Lastly, here's the graph that the ring oscillator produces.

Lab
For the lab, I first created an 4-bit inverter. Then, I created 8-bit input/output array of the NAND, NOR, AND, inverter, and OR gates.
After that, I created an 8-bit wide DEMUX/MUX schematic and symbol. Finally, I designed the schematic and layout for an 8-bit full-adder that utilized 6u/0.6u NMOS and PMOS devices.

4-bit Inverter
First, let's start with the 4-bit inverter.

1-bit Inverter Schematic

1-bit Inverter Symbol

4-bit Inverter Schematic

4-bit Inverter Symbol

Simulation Schematic

Graph

Based on the graph, a larger capacitance value leads to a more smooth rise and fall of the voltage.

8-bit NAND Gate
1-bit Transistor Level Logic

Schematic

Symbol

8-bit NOR Gate
1-bit Transistor Level Logic

1-bit Nor Symbol

Schematic

Symbol

8-bit AND Gate
Schematic

Symbol

8-bit OR Gate

Schematic

Symbol

Simulation of NAND, NOR, AND, inverter, and OR gates

Schematic

Graph

DEMUX/MUX

Next, I created a demux/mux circuit.

Schematic

Symbol

Schematic for simulation of MUX

Graph

A mux basically chooses which input signal passes through. In the case of the one I built, when S is 1, A is outputted to Z. When Si is 1, B is outputted to Z.

Simulation of DEMUX

I added capacitors to outputs A and B to save the previous values.

Graph

The demux basically does the opposite of the MUX. Z is the input that determines the value of the outputs A and B. When S is 1, A outputs Z's value. When Si is 1, B outputs Z's value.

8bit 2 to 1 MUX

1bit MUX Schematic

1bit Symbol

8bit Schematic

8bit Symbol

Simulation Schematic

Simulation Graph

When S is 1, Z outputs A which is 0. When S is 0, Z outputs B which is 1.

8bit 2 to 1 DEMUX

Simulation Schematic

Graph

Depending on whether S is 1 or 0, that determines whether Z is written to the A output array or the B output array. When S is 1, Z is outputted to A. When S is 0, Z is outputted to B.

8-bit Full-adder

For the final portion of the lab, an 8-bit full adder will be created that is based upon the topology shown in Fig. 12.20 in Dr. Baker's Circuit Design Textbook.

1-bit Schematic