Lab Project

Lab Project - EE 421L

Author: Kaione Daniels

Email: daniek8@unlv.nevada.edu

November 20, 2021

Lab Project Description

-In this project, a register file (RF) was designed that contains 32 words. Each word contains 8-bits.

-The RF utilized a 5-bit address in order to determine which of the 32 words are being accessed.

-8 input and output lines will be utilized for reading and writing.

-In addition, a control signal and read/write lines will also be routed.

-Finally, VDD/GND inputs will be available.

Designing the Register File

SRAM Cell

-First, I started with designing a single SRAM (Static Random Access Memory) cell that contains only 1 bit of data each.

-The SRAM cell contains inverters that contain small transistors (1.5u/1.5u). This is because small transitors allow the cell to be flipped more easily.

-Di, which is the complement of D, is an integral part of the SRAM cell because NMOS transistors do not pass "1" values well.

-Regardless of whether D is "1" or "0", either D or Di will pass through the NMOS updating the SRAM cell in the process.

Below is a picture of an SRAM cell schematic. When the row line becomes "1", this allows the NMOS on each side of the cell to turn on.

This allows the cell to be updated to the value contained in the data line (D).

SRAM Schematic

The symbol contains three pins. These are the row line and the data lines.

SRAM Symbol

Next, the layout of the SRAM cell was performed. The corresponding extracted version is also shown below. The same number of transistors in the schematic are present in the extracted.

SRAM Layout	SRAM Extracted

I then ensured that the layout passed the DRC (Design Rule Check) and LVS (Layout Versus Schematic).

SRAM DRC	SRAM LVS

SRAM Cell Simulation
Below are the simulations for the SRAM cell.

SRAM Cell Simulation Schematic

SRAM Cell Simulation Graph

From the graph, we can see that the SRAM cell is indeed storing the data value when row is high.

8-Bit Word

Next, I integrated 8 SRAM cells into one schematic. This was done by leveraging cadence's array feature which allows the user to duplicate a single instance multiple times.

In this case, I duplicated the SRAM cell 8 times.

Below is a picture of the 8-bit word schematic.

8-Bit Word Schematic

An 8 bit data lines and its complement are ran into the word cell along with a row line which determines whether the cell is activated or deactivated.

8-Bit Word Symbol

Next, here is the layout of the Word. The layout is basically just 8 SRAM cells that have been duplicated.

8-Bit Word Layout

Below is the extracted version.

8-Bit Word Extracted

Lastly, I ensured that the 8-Bit Word passed the DRC and LVS check.

8-Bit Word DRC	8-Bit Word LVS

8-bit Word Simulation
Below are the simulations for the 8-bit word cell.

8-bit Word Simulation Schematic

8-bit Word Simulation Graph

From the graph, we can see that the SRAM cell is indeed storing the data value when row is high.

32 Word Array

-Next, I duplicated the 8-Bit Word cells 32 times to create the 32 Word Array. This array is basically where all the memory will be stored.

-The 32 row lines come from the row decoder which will be covered in the next section. The row bus basically determines which word cell turns on.

-When a cell turns on, this means that the SRAM can be updated.

Below is a picture of the schematic. I leveraged Cadence's array feature in order to duplicate the 8-Bit Word cell 32 times.

32 Word Array Schematic

Here is the Symbol.

32 Word Array Symbol

Below are the layout and extracted versions of the 32 Word Array. I decided to stack the Word cells vertically on top of each other.

32 Word Array Layout	32 Word Array Extracted

Finally, here is evidence that the design passes the LVS and DRC check.

32 Word Array DRC	32 Word Array LVS

32 Word Array Simulation
Below are the simulations for the 32 word array.

32 Word Array Simulation Schematic

32 Word Array Simulation Graph

From the graph, we can see that the SRAM cell 0 is indeed storing the data value when row is high.

NAND gate with 5 inputs

The final part of the Register File is a row decoder; however, we must first create an NAND gate that can handle 5 inputs and provide one output.
The boolean logic is: out = A'+B'+C'+D'+E'

Below is a picture of the schematic.

NAND Gate Schematic

Here is the Symbol.

NAND Gate Symbol

Below is the layout of the NAND Gate.

NAND Gate Layout

Here is the extracted of the NAND Gate.

NAND Gate Extracted

Finally, here is evidence that the design passes the LVS and DRC check.

NAND Gate DRC	NAND Gate LVS

NAND Gate Simulation
Below are the simulations for the NAND Gate.

NAND Gate Simulation Schematic

NAND Gate Simulation Graph

From the graph, we can see that the NAND gate is high when every input is not a "1". When all inputs are a "1", the output is "0".

AND gate with 5 inputs

Now, we will integrate the NAND gate in our AND gate design by attaching an inverter to the end.
The boolean logic is: out = A*B*C*D*E

Below is a picture of the schematic.

AND Gate Schematic

Here is the Symbol.

AND Gate Symbol

Below is the layout of the AND Gate.

AND Gate Layout

Here is the extracted of the AND Gate.

AND Gate Extracted

Finally, here is evidence that the design passes the LVS and DRC check.

AND Gate DRC	AND Gate LVS

AND Gate Simulation
Below are the simulations for the AND Gate.

AND Gate Simulation Schematic

AND Gate Simulation Graph

From the graph, we can see that the AND gate is high when every input is a "1". When all inputs are not a "1", the output is "0".

Row Decoder

-Finally, we can now move onto the row decoder after making the 5 input AND gate.
-Basically, the row decoder will choose which 8 Bit Word Cell will be activated.
-This will be determined by the value of the 5-bit address. Each possible address corresponds to one of the 8 Bit Word Cells.

Below is a table that dispays which row is activated based on the address.

Address (A4-A0)	Row
00000	0
00001	1
00010	2
00011	3
00100	4
00101	5
00110	6
00111	7
01000	8
01001	9
01010	10
01011	11
01100	12
01101	13
01110	14
01111	15
10000	16
10001	17
10010	18
10011	19
10100	20
10101	21
10110	22
10111	23
11000	24
11001	25
11010	26
11011	27
11100	28
11101	29
11110	30
11111	31

Below is a picture of the schematic.

Row Decoder Schematic

Here is the Symbol. The symbol contains the 5-Bit Address and the 32-Bit row bus.

Row Decoder Symbol

Below is the layout and extracted view of the Row Decoder.

Row Decoder Layout	Row Decoder Extracted

Since the layout/extracted are so large, here is a more in depth view of the Row Decoder.

AND Gate Connections Layout	AND Gate Connections Extracted

Inverters for the Address Layout	Inverters for the Address Extracted

Here is an example of the AND gate input connections.

Example of AND gate connections in Layout

Finally, here is evidence that the design passes the LVS and DRC check.

Row Decoder DRC	Row Decoder LVS

Row Decoder Simulation
Below are the simulations for the Row Decoder.

Row Decoder Simulation Schematic

Row Decoder Simulation Graph

When ABCDE = 11110, Row<30> turns on while all other rows are off. When ABCDE = 11111, Row <31> turns on.

Finally, all the components of the register file have been created. These components were:
-SRAM
-8-Bit Word
-32 Word Array
-Row Decoder

The only new component in the RF is the R_W signal. This signal determines whether the RF will either read or write. Read is "1". Write is "0".

-When R_W is "0", the NMOS for Data Input (DI) turns on which updates one of the 8-Bit Word Cells.

-When R_W is "1", the NMOS for the Data Output (DO) turns on which causes one of the 8-Bit Word Cells to output its data.

Now, all of these components will be integrated together. Below is the schematic.

RF Schematic

Here is the Symbol.

RF Symbol

Below is the layout of the RF.

RF Layout	RF Extracted

Here is a closer view of the NMOS transistors that were added in the RF.

NMOS for RW Layout

NMOS for RW Extracted

Finally, here is evidence that the design passes the LVS and DRC check.

RF DRC	RF LVS	RF Netlist

With the register file successfully created, we can now move on to the testing portion.

RF Simulation Schematic

For the sake of simplicity, I decided to hold a static address which was 11111. In addition, only a single bit of the data will be toggled. In this case, it is DI[0]. Lastly, RW will be toggled.

Test Overview

-Address = 11111

-DI[0] toggles between 0 and 1.

-RW toggles between 0 and 1.

-D Output is the output of the RF.

-"SRAM Value" is the value present within the SRAM cell.

Below is a graph of the simulation.

RF Simulation Graph

-When the RW changes to "0", this causes the RF to enter write mode. This means that the value of DI[0] will be written into Address 11111 cell 0.

-When the RW changes to "1", this causes the RF to enter read mode. This means that the value in Address 11111 cell 0 will be outputted to DO[0].

-As we can see from the simulations, the SRAM value of Address 11111 Cell 0 is indeed being updated when the RF enters write mode. In addition, the SRAM value is also saved when the RF enters read mode.

-In addition, the D Output is also being updated correctly. Whenever write mode is enabled, the SRAM value is outputted.

Problems with the Current RF Design

-Even though the output may be correct for the D output, there are still some flaws.

-For instance, D Output only reaches a maximum value of around 4.1 V for a "1" which is not good. Ideally, this value is 5V for a "1".

-The 4.1V is caused when you do VDD - VTHN. Basically, when a high passes through an NMOS, this causes the 5V to be reduced by the Voltage Threshold of the NMOS. This is the reason why NMOS transistors do not pass high values well.

-In order to fix this, you would need to implement charge pumps on the row lines so that the gates can be yanked up which causes a full logic signal to output. However, this is beyond the scope of the Digital IC Design Course.

RF Zip File

Click here to access the zip file for the RF.

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