Lab 5 - EE 421L 

Author: Kaione Daniels 

Email: daniek8@unlv.nevada.edu

September 22, 2021 

  

Lab Purpose

The purpose of Lab 5 is to design, layout, and simulate two different CMOS inverters.
The first inverter will have a PMOS/NMOS width size of 12u/6u. The length of both devices will be 0.6u.
The second inverter will havea  PMOS/NMOS width size of 48u/24u. The length of both devices will be 0.6u.

  

Prelab
For the prelab, I went through tutorial 3 which consisted of the creation of a CMOS inverter. The schematic, symbol, layout, and simulation were covered in the tutorial.
         

Lab

12u/6u Inverter

First, I created the schematic for the 12u/6u CMOS inverter. 

       

Next, I utilized the schematic to create the symbol.

       

After that, I created the layout.

         

Finally, I extracted the layout.

       

Below is proof that the layout is LVS and DRC clean.

       

48u/24u Inverter

First, I created the schematic for the 48u/24u CMOS inverter. 

         

Next, I utilized the schematic to create the symbol.

     

After that, I created the layout.

     

Finally, I extracted the layout.

     

Below is proof that the layout is LVS and DRC clean.

         

Spectre Simulations

For the next part of the lab, I simulated the 12u/6u inverter driving a 100fF, 1pf, 10pF, and 100pF capacitive load.

   

100fF



      

1pF

       

10pF

       

100pF



   

After that, I simulated the 48u/24u inverter driving a 100fF, 1pf, 10pF, and 100pF capacitive load.

     

100fF

     

1pF

       

10pF

     

100pF

     

Conclusion

A higher capacitance will result in a slower transition for the output. The change in output is dampened for higher capacitance values. 

The 48u/24u inverter caused the output to transition quicker due to the fact that the resistance of a larger MOSFET is lower. 

On the other hand, the 12u/6u inverter caused the output to transition lower since the resistance of this smaller MOSFET is higher.

The time delay is directly influenced by the resistance value which means that a higher resistance will result in a higher time delay and vice versa.

       

Ultrasim Simulations

For the last part of the lab, I simulated the 12u/6u inverter driving a 100fF, 1pf, 10pF, and 100pF capacitive load using the Ultrasim model. 

Ultrasim is the fastest SPICE simulator in Cadence; however, this speed comes at a cost. The simulation will not be as accurate as the Spectre model.

100fF

     

1pF

     

10pF

     

100pF

     

After that, I simulated the 48u/24u inverter driving a 100fF, 1pf, 10pF, and 100pF capacitive load.

     

100fF

     

1pF

     

10pF

     

100pF

       

Click here to download the Lab5.zip file.

     

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