EE 421L - Digital Integrated Circuit Design Lab
     

Author: Abraham Lopez

Email: lopeza43@unlv.nevada.edu
Fall 2020

     
Laboratory Reports
     

Laboratory

Title

Lab 1

Laboratory introduction, generating/posting html lab reports, installing and using Cadence

Lab 2

Design of a 10–bit digital–to–analog converter (DAC)

Lab 3

Layout of a 10–bit DAC

Lab 4

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Lab 5

Design, layout, and simulation of a CMOS inverter

Lab 6

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder

Lab 7

Using buses and arrays in the design of word inverters, muxes, and high–speed adders

Lab 8

Generating a test chip layout for submission to MOSIS for fabrication

Project

High-speed Digital Receiver

   
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