Lab Project - EE 421L Fall 2020
   
Authored by Abraham Lopez on 11/17/20
Email: lopeza43@unlv.nevada.edu
 
   
Project description
The purpose of this lab project is to design, simulate, and layout a high speed receiver circuit.
The circuit has to be capable of accepting a pair of high speed differential signals, where the
two signals are complements of each other. For example, if D is a higher voltage than Di then the
circuit outputs a 1. Likewise, if Di is greater than D then it outputs a 0. While designing the circuit
it is also important to consider trade-offs in terms of power and speed. Where if the circuit can
perform at higher speeds, it can be better at matching the switching points of the input signals,but at the
cost of using more power. Otherwise, the circuit can use less power by performing at a lower speed,
but at the cost of being more delayed at the switching points of the signal.
 
Part 1: Picking a Design
To start off the project there are three possible topologies for the design. There is an N-type, P-type,
and Rail input buffer to chose from and at certain conditions each can work differently.
 
N-type input buffer schematic

This design is composed of the N-type self biased diff-amp and buffered with two inverters to stable the output. The circuit works when a
voltage is applied to both Vinm and Vinp, then when Vinm is greater than Vinp the current running through the NMOS of Vinm is going to
be greater than the current running the NMOS of Vinp. The current will flow to the PMOS above the NMOS and is mirrored by PMOS across
from it. This current will be greater than that of the NMOS of Vinp which causes Vom to be pulled high to VDD.
 
Simulation of N-type buffer at VDD = 5 V, Vdiff = 1 V, freq = 100 MHz, bit width = 250 Mbits/s

 
Results


From the simulation results, when tested with the parameters above the N-type buffer performs as
expected by being to output full logic level signals when Vinm is greater than Vinp. Also it is able to
output those logic levels with little delay from the input signals with the tpLH and tpHL being
531 ps and 685 ps.
   
However, the N-type design has a trade off where as the lower the voltage difference is between the
two input signals the circuit outputs at a lower speed. The voltage this occurs at is 250 mV and the reason its
this voltage is because this is the threshold voltage of the MOSFETs meaning once the voltage difference is at or
below 250 mV the MOSFETs will operate in the sub threshold region, hence the longer delays. This can be seen in
the simulation below where the tpHL is 1.4 ns.
   
Simulation of N-type buffer at VDD = 5 V, Vdiff = 200 mV, freq = 100 MHz, bit width = 250 Mbits/s

From these results it can be inferred that the N-type buffer is not the optimal topology to use for this
project. Instead let's see if the P-type buffer is the better choice to use in this project.
   
P-type buffer schematic

The P-type buffer works in the same manner as the N-type buffer, where as Vinm is greater than Vinp, the current flowing through the NMOS
below the PMOS of Vinp causes it to be pulled high to VDD.
   
Simulation of P-type buffer at VDD = 5 V, Vdiff = 1 V, freq = 100 MHz, bit width = 250 Mbits/s

   
Results


These results are very similar compared to the N-type, which is to be expected, with a Vdiff of 1 V
it should be easy for both circuits to output quickly when the inputs change, but let's see if this holds
true for when Vdiff is below 250 mV.
   
Simulation of P-type buffer at VDD = 5 V, Vdiff = 200 mV, freq = 100 MHz, bit width = 250 Mbits/s

Looking at the results, the tpLH is much better than when the N-type was simulating, but there is now
a relatively large offset of about 2 ns from when the input signals switch. The value of this delay is too
large to use for our project, so this rules using the P-type for the project, which now leaves one option left
the Rail type buffer.
   
Rail type buffer schematic

The rail type buffer is composed of both the N-type and P-type diff-amps connected parallel to each other. This type of topology allows for a good combination of different voltages for the rail type buffer to operate at, making it ideal for this project.
   
Simulation of Rail type buffer at VDD = 5 V, Vdiff = 1 V, freq = 100 MHz, bit width = 250 Mbits/s

 
Results


Running the simulation at the same parameters as the previous buffers were tested at results in similar results with the rail type having slightly better delays.
   
Simulation of Rail type buffer at VDD = 5 V, Vdiff = 200 mV, freq = 100 MHz, bit width = 250 Mbits/s


This is were the rail type buffer really show its advantage. When the Vdiff is below the voltage threshold the rail type is still able to deliver full logic levels at a good speed, as the delays are larger than when the Vdiff was 1 V,but  it is much better compared to the N-type and P-type buffers when they were operating at the same difference.
   
Now that the optimal topology has been selected, there is one more design decision left for the circuit and that is selecting the size of the MOSFETs. For most of the NMOS and PMOS devices they will be sized at 12 um and 6 um for the widths and 600 nm for the length. This is not the case however for the NMOS and PMOS at the bottom and top of the circuit as moving the length and the widths of these MOSFETs can impact the speed of the output of the circuit and the amount of power the circuit dissipates. With this knowledge in hand, it is best to pick a length and width where the output will have a high speed, but use less power. The simulations below will help in deciding what is the more optimal size for the MOSFETs.
   
PMOS Width = 12 um, NMOS Width = 6 um, Both have a of Length = 600 nm


 
 
PMOS Width = 12 um, NMOS Width = 6 um, Both have a of Length = 1.2 um




   
PMOS Width = 12 um, NMOS Width = 6 um, Both have a of Length = 2.4 um



The results of the simulations confirm that changing the length to a larger value will slow down the speed
of the output, but decrease the amount of power used in the circuit. While a smaller length will give a faster,
but it needs more power to do so.
   
PMOS Width = 18 um, NMOS Width = 9 um, Both have a of Length = 1.2 um


 
PMOS Width = 9 um, NMOS Width = 6 um, Both have a of Length = 1.2 um


Changing the widths of the MOSFETs by increasing the width causes more delay and more power
to be used. While a smaller width uses less power, but at the cost of a even larger delay compared
to making the width bigger. Therefore, for this project only the length of the MOSFETs will be
changed.
 
Final Design of Rail type buffer

The final design for our project is the rail input buffer with the top PMOS and bottom NMOS
both have a length of 1.2 um. While having the widths of 12 um and 6 um.
   
Part 2: Simulating different VDDs, Vdiffs, input frequencies, and temperatures
   

VDD	Simulation
5 V
4 V
3.5 V
3.4 V
3 V

It seems that at a Vdiff of 200 mV, the circuit works fine at 5 V for VDD as expected. At 4 V, however the circuit is still working as intended
with the output going high and low when the input signals change, but the voltage of the logic level  is now at 4 V instead of 5 V. This statement
applies to VDD at 3.5 V. Now at 3.4 V the circuit is no longer working as intended with the output starting to be pulled to whatever voltage VDD is
and is confirmed when VDD is 3 V as the output starts to remain constant, as the MOSFETs are not being turned on.
 
 

Vdiff	Delay tpLH and tpHL	Simulation 1	Simulation 2
1 V	549 ps and 558 ps
0.5 V	640 ps and 682 ps
0.25 V	775 ps and 836 ps
0.125 V	1.1 ns and 1.06 ns
0.0625 V	1.3 ns and 1.2 ns

When it comes to the circuit be able to detect the voltage difference between the two input signals it appears that as the difference becomes smaller and smaller the circuit will take longer to output a high or low. This is to be expected as the design was made to work at lower input voltages, however it still has limits as at some point the voltage will be to small for the MOSFETs causing to enter sub threshold mode. Eventually, if the voltage continues to get smaller the MOSFETs will turn off and this appears to start to happen at 0.0625 V, where the logic levels are no longer 5 V and 0 V. This is actually a good result as the circuit is able to at least detect the voltage difference within a 1/16 of a volt.
 
 

Power	Frequency	Simulation	Calculation using average(I(VDD))*VDD
-7.38 mW	100 MHz with a bit width of 250 Mbits/s
-6.95 mW	56 MHz with a bit width of 125 Mbits/s
-7.94 mW	167 MHz with a bit width of 500 Mbits/s

Looking at these simulations, it is apparent the relationship frequency has with power. As our inputs have higher frequencies then the more power the circuit will use in order to keep the output up with the switching points of the inputs. While the lower the frequency the less power is used. The average power can be calculated and prove this by using the equation of Pavg = average(I(VDD)*VDD in the cadence calculator, where the average power the circuit uses equals the average current flowing into the power supply of VDD then multiplied by VDD. 
 
 

Frequency	Delay of tpLH and tpHL	Simulation 1	Simulation 2
100 MHz with a bit width of 250 Mbits/s	827 ps and 883 ps
125 MHz with a bit width of  333 Mbits/s	827 ps and 881 ps
200 MHz with a bit width of 667 Mbits/s
250 MHz with a bit width of 1 Gbit/s	831 ps and 860 ps

Testing at different frequencies of 100, 125, 200, 250 MHz with corresponding bit widths of 250 Mbits/s, 333 Mbits/s , 667 Mbits/s and
1 Gbit/s all have similar delays and perform well by keeping around 850 ps from the inputs switching, however at 1 Gbit/s the output looks to be at the halfway point of the pulse width as it is now smaller. Which can cause problems if the output does not go high or low until halfway into the bit width. It can be said then that the design does not work for a high speed of 1 Gbit/s, but it does work for up to a speed of
667 Mbits/s which is good, as the target value given was 250 Mbits/s.
   
Parametric simulation of temperature of the Rail type buffer

Doing a parametric analysis, from 0 ºC to 100ºC, of the circuit reveals that at lower temperatures the circuit performs a bit better as the delays are slightly smaller and at higher temperatures the circuit output is a bit more delayed.
 
End of Part 1 of Lab project
                                                                                       
   
Part 2 of Lab project
   
Layouts
The second part of the lab invloves designing the layout for the Rail type buffer, while also making sure the layout
DRCs with no errors and passes LVS verification.
   
Schematic of the Rail type buffer

   
Layout of Rail type buffer

   
DRC of Layout

   
LVS of Layout

 
Copy of design files
A copy if the design Files for the lab project can be downloaded here.

This concludes the lab project.
   
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