Emails: alvara6@unlv.nevada.edu , lopeza43@unlv.nevada.edu,
callab2@unlv.nevada.edu
December 2,
2020
Lab Description
Generating a test
chip layout for submission to MOSIS for fabrication
·
This
lab teaches how to layout circuits onto a chip for fabrication. This lab shows
how to create a pad frame, and how to connect the components of the layouts to
the pad frame.
Pre - Lab
- Back-up
all of your work from the lab and the course.
- Go
through Cadence Tutorial 6 seen here.
- Read through the lab
in its entirety before starting to work on it
Going through Tutorial 6
The pictures
above are showing the critical steps of tutorial 6. The first snip shows the
making of the pad, the next snip shows the pad frame with the 40 pins. The next
snips are showing
the
input/outputs connecting to the pad, finally we are showing the symbol that was
have created for the pad.
Lab Tasks
Your chip should include the following test structures:
- A 31-stage ring oscillator
with a buffer for driving a 20 pF off-chip load
- NAND and NOR gates
using 6/0.6 NMOSs and PMOSs
- An inverter made with
a 6/0.6 NMOS and a 12/0.6 PMOS
- Transistors, both
PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are
connected to bond pads (7 pads + common gnd pad)
- Note that only one
pad is needed for the common gnd pad. This pad is used to ground the
p-substrate and provide ground to each test circuit
- Using the 25k
resistor laid out below and a 10k resistor implement a voltage divider
(need only 1 more pad above the ones used for the 25k resistor)
- A 25k resistor
implemented using the n-well (connect
between 2 pads but we also need a common gnd pad)
Lab
Course Project(s)
Lecture
Project
The snips
above are demonstrating the lecture project (symbol, layout view) which was a
controller chip for a fly back SPS. Pin 15 is the VDD of the project,
pin 16 is the
Vfp, while pin 10 is the output.
Lab Project
The snips
above are the lab project which was a high-speed digital receiver. The snips
include the schematic, the symbol with the connect pins for the pad, the
layout,
and the layout
attached to the pad frame. Pin 34 and pin 35 are the inputs of the receiver,
and pin 36 is the output of the receiver.
31 Stage Ring Oscillator + Buffer
The snips
above are the schematic, layout, schematic for the pad frame showing the pins,
and the final snip is showing the layout connected to the pad frame.
Pin 1 is the
input of the ring oscillator, pin 2 is the vdd for the buffer, and pin 3 is the
output of this combination.
NAND and NOR
gates using 6/0.6 NMOSs and PMOSs
The snips above are showing the NAND and NOR gates which use
6/0.6. The snips show the schematics, the symbol which shows what pins are
connected to the pad frame, the layouts, and the layouts connected to the pad
frame.
An inverter
made with a 6/0.6 NMOS and a 12/0.6 PMOS
Inverter made with 6/0.6 NMOS and 12.0/.6 PMOS. The schematic,
this symbol with the pin to the pad frame demonstrated, the layout, and the
layout connected to the pad frame.
Using the 25k
resistor laid out below and a 10k resistor implement a voltage divider
Schematic, symbol, layout and layout of the voltage divider
connected to the pad frame displayed above.
A 25k resistor
implemented using the n-well
Schematic, symbol, layout, and layout of the 25k resistor
connected to the pad frame displayed above.
Transistors, both PMOS and
NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to
bond pads
These snips
are displaying the PMOS and NMOS schematics, with their respective symbols,
layouts, and layouts attached to the pad frame.
Final Chip Assembly
The open
pins were 1- 20,34-40 with pin 20 reserved for gnd!, and pin 33 reserved for
vdd!.
Here is the
final schematic showing all the components connected to the pad frame, this
also shows all the components and the pins that they were assigned.
The second
snip demonstrates the final product with all the layouts attached, completing
the chip.
Verification
that the chip works. The first snip is showing the DRC and the second shows
that the chip LVSs.
Summary of Pins
Pin 1 Input
of the Ring Oscillator
Pin 2 Vdd
for the Buffer
Pin 3 Output
of the Ring Oscillator + Buffer
Pin 4 No
Connection
Pin 5 - No
Connection
Pin 6 Output
of the Inverter
Pin 7 Vdd of
the Inverter
Pin 8 Input
of the Inverter
Pin 9 Input
or Left side of the Resistor
Pin 10
Output of the Lecture Project
Pin 11 Body
Connection to the PMOS
Pin 12
Source Connection to the PMOS
Pin 13 Gate
Connection to the PMOS
Pin 14 Drain
Connection to the PMOS
Pin 15 Vdd
for the lecture Project
Pin 16 Vfp
for the lecture Project
Pin 17
Output voltage of the voltage divider
Pin 18 Input
voltage of the voltage divider
Pin 19 - No Connection
Pin 20 Gnd
pin
Pin 21 - No
Connection
Pin 22 Vdd
for the Nand gate
Pin 23 Input
A of the Nand Gate
Pin 24 Input
B of the Nand Gate
Pin 25
Output of the Nand Gate
Pin 26 - No
Connection
Pin 27 - No
Connection
Pin 28 Input
A of the Nor Gate
Pin 29
Output of the Nor Gate
Pin 30 Vdd
for the Nor Gate
Pin 31 Input
B of the Nor Gate
Pin 32 - No
Connection
Pin 33 Vdd
of the Comparator
Pin 34 Input
A of the Comparator
Pin 35 Input
B of the Comparator
Pin 36 Output
of the Comparator
Pin 37
Source Connection to the NMOS
Pin 38 Drain
connection to the NMOS
Pin 39 Gate
connection to the NMOS
Pin 40 - No
Connection
Backing Up Work
First, I found the tutorial folder in my CMOSedu folder
in the MobaXTerm.
After finding where the folder was, I downloaded the folder to the
desktop and later sent it to a compressed zipped folder.
After making a ZIP file I uploaded them to my google drive with
the date in the title. This should complete my backup process.
This concludes Lab 8.
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to Armanis Lab Reports