Lab 5 - EE 421L Fall 2020
   
Authored by Abraham Lopez on 09/22/20
Email: lopeza43@unlv.nevada.edu
   
Design files for lab 5 are found here.
   
Lab description
The purpose of this lab was to draft schematics, symbols, and layouts of two different sized
inverters of 12u/6u and 48u/24u. Then to test through simulations both inverters at different capacitive loads.
   
Pre-lab
For this pre-lab we had to back up our previous work, read through the lab guide, and go through Tutorial 3.
   
We start of by creating a new library for tutorial 3 by copying the library for tutorial 2 and renaming it.
Then using the PMOS and NMOS designs from tutorial 2 we can copy them into a new schematic cell named
inverter. We can do this by using "c" to copy the schematic, clicking on hide, and then with two windows open
next to each other, we can copy into the inverter schematic cell.
   
   
We then connect the NMOS and PMOS together, as seen below, with the PMOS having a size of 12 um and the NMOS a size of 6 um.
Also we instantiate "vdd" and "gnd" to complete the circuit, along with pins of A and Ai for the input and output respectively.

   
Next we create a cell view for the symbol of the inverter.

   
After that we want to create a layout cell and instantiate a PMOS of 12um, NMOS of 6um, ptap, ntap, and m1_poly.
To create the inverter , we connect the poly of the NMOS and PMOS together, then connect the poly to the metal 1 contact
, labeled as A. Next we connect the source of the NMOS to the ptap, which is labeled as gnd!, and the drain of the PMOS to the ntap
, labeled vdd!. Finally, we connect together the source of the PMOS and the Drain of the NMOS for the output Ai.

 
After the layout is done we DRC, extract and LVS the layout.

   

 
Then taking our symbol we made earlier, we create a new schematic cell for simulation and
connect it as seen below.

 
Starting up the ADE, we want to set up a sweep variable of V0, set up the models libraries of the MOSFETS,
and set up a dc sweep, as seen below.

 

   

   
For this simulation we also want to make sure that we set a Stimuli for vdd, otherwise the inverter won't work properly.

   
Now we simulate the circuit and see the results.

   
Finally we simulate the extracted layout of the schematic.

   

   
Lab Procedures
1. Drafting a schematic, layout, and symbol for 12u/6u inverter.
   
For this first procedure we are doing most of the same steps from the tutorial. First, we want
to create a lab 5 library and copy the schematic of the inverter from tutorial 3 into the cell for lab 5.

   
Then we create a symbol for the inverter, along with some test that tells the size of the inverter.

   
Once that is done, we layout the inverter.

 
Now we DRC, extract, and LVS the layout.

 

 
2. Drafting a schematic, layout, and symbol for 48u/24u inverter.
   
Taking our inverter schematic from early, we want to copy it into a new cell and change the multiplier value to 4 (m=4).

 
Creating a symbol for the 48u/24u inverter.

 
Now we layout the inverter and to do this we want to take one 12um PMOS and layer it on side to side in order to create a 48 um PMOS.
We also want to do the same for the NMOS and connect the terminals of the MOSFETs to their respective place, as seen below.

   
After the layout is done DRC, extract, and LVS the design.

 

   
3. Simulating the inverters
 
The first simulation we are going to do is the inverter of 12u/6u and we want to create the following schematic seen below.

 
Settings for Vpulse.

 
Starting up the ADE, we want to run a transient analysis while using a parametric analysis for the capacitor in
order to simulate the circuit at different loads.

 

   
Simulation results of inverter at different capacitive loads.

   
Looking at the simulations we notice that as the input is at low voltage, then the output is high. Then when the input is high the output goes low
and this depends on the capacitive load that is attached to the inverter. With a smaller capacitance the fall and rise times are lower. While with
a bigger capacitance the rise and fall times are much greater.
   
Now we want to do the same for the 48u/24u inverter by creating the schematic.

 
Simulating the circuit with the same options from before.

   
With a bigger sized inverter the input and output still function the same while the input is low, then the output is high and vice versa.
However, the bigger size of the inverter does effect the rise and fall times increasing them significantly. We can say that increasing the
size of the inverter increases the inverting effect of the inverter.
 
4. Simulations with UltraSim
   
We now want to repeat the simulations we just did except with the UltraSim simulator. Note we have to
set up the model libraries of the MOSFETs again.

 
How to check that simulation is using UltraSim.

 

   
Simulations of 12u/6u and 48u/24u inverter using UltraSim.

   

   
Both inverters simulated with UltraSim seem to show no difference between the previous simulations.
   
Saving the UltraSim states.

 

   
4. Backing up work
 
I downloaded and zipped up a copy of the lab5 folder.

   
Then sent an email of the file to myself under the label "lab 421 work".

   
Design files for lab 5 are found here.
 
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