Lab 2 - EE
421L FALL 2020
Authored by Abraham Lopez on
09/06/2020
Lab description
Pre-Lab
The pre-lab involved downloading the
lab2.zip from the lab 2 page and uploading it into the CMOSedu folder in
MobaXterm, then
unzipping it using unzip
lab2.zip in the terminal.
After unzipping the file, the next step was to open the cds.lib with a text editor and add the following line “DEFINE lab2
$HOME/CMOSedu/lab2” to the file to make sure it was
readable in cadence.
Once those steps are
done, we can start cadence and open the lab 2 library and click on the
schematic view of “sim_ideal_ADC_DAC” cell.
For this next part of the pre-lab we need to use different simulations
in order to understand how the input voltage, Vin, is related to B[9:0]
and Vout, while also
determining the least significant bit (LSB, the minimum voltage change on the ADC's input to see a change in
the digital code B[9:0]). First, we will start with loading the save state that
was already with the schematic and running it to get an idea of how everything
relates.
Looking
at this first simulation doesn’t seem to help, as there are no many steps to
get an idea of what’s going on, so let’s look at how the LSB can be calculated
from the formula provided in the pre-lab.
Where
VDD is 5V from the lab and 2N, which is the bit width, and N equals
10 as B[9:0] represents a 10-bit output. Plugging in
everything we get the following
1 LSB = 5V / 210 = 4.88mV
We now
know that the minimum voltage change for each step or
the LSB is 4.88mV, now with this information let’s change the properties of our
voltage source Vin. Currently Vin is using an amplitude of 2.5V and a DC offset
of 2.5V, let’s change the amplitude to around the same voltage of the LSB which
is 5mV and see the results.
Looking
at the voltage steps of Vout we see the voltage difference from the two marked
steps is 2.50488 – 2.5 = 4.88mV. This is a good indication that the
LSB is indeed 4.88mV, but let’s run another simulation with a voltage source
that is exactly 4.88mV. To accomplish this, we’ll change the amplitude and DC
offset to 2.44mV and see the results.
Looking
at the simulation we can now confidently verify the step size is 4.88mV.
With all this information let’s answer the following questions provided from
the pre-lab in lab 2.
1) Provide and discuss your understanding of the ADC and
DAC.
The ADC receives an
analog input, in this case Vin, and converts that input into binary code. This
binary number is the output of the ADC and is received by the DAC as binary
code
where the DAC takes the binary code and converts it to an analog waveform.
2) How is Vin related to B[9:0] and Vout?
Vin as an analog source goes into the ADC , where it is
converted into binary number B[9:0] as it is the 10-bit binary representation value of Vin. Where each wire of the B[9:0]
represents a different digit of the 10-bit binary representation of Vin, with
B0 being the least significant bit and B9 being the most significant bit. This
10-bit binary number goes into the DAC to be reconverted into an analog output
which is Vout.
3) Explain how you determine the least significant bit. Use simulations to
support your understanding.
We determined the LSB by using the equation given in the pre-lab of 1 LSB = VDD
/ 2N, where when plugging in our VDD and N, we calculated 4.88mV. We
then verified this calculation by changing the amplitude and offset of Vin to
get a 4.88mV source and the resulting simulation seen above confirmed our
calculation.
Lab
Procedures
1. Design of a 10-bit DAC using an n-well resistor of 10K
For
this first part of the lab we created a schematic and symbol of an n-well
resistor of 10k. Which is a voltage divider with three resistors of 10k and
three pins representing input, output, and the carry bit.
To create a symbol for a schematic, click on the “Create” tab
on the top of the menu then click on “cellview” and “from cellview”.
Now that we have a symbol of the n-well resistor we can use the command “i” to
instantiate the symbol from the lab2 library and
create a schematic of a 10-bit DAC by connecting 10 of them together and
creating a symbol for it.
2. Verifying and Testing 10-bit DAC
For this next part we needed to do some hand calculations in order to find the
overall resistance R of the DAC and then the time delay when using it
with a 10pF capacitor and 0V to 2V pulse.
To find the overall resistance R, we ground every input except B9 and combine
all the resistors in series and parallel until we are left with R which is 10k.
We then take that R and use it to find the delay which is 70ns. We can then
confirm these calculations with the schematic and simulation seen below, where
at half of the charged output voltage, which is .5V, we have a delay of 70ns.
Before we start testing the DAC with loads, we need to create our own “sim_ideal_ADC_DAC” cell to use for
our DAC. This can be
easily accomplished by copying and renaming the cell.
Then once we open our copied cell we want to click on the DAC that’s currently there and press q to change its name to the name of our DAC
which will replace it. Also, we want to delete VDD, Verfp, or Vrefm from the DAC as we won’t be
using those pins.
We also need to change a few things in the simulation options in order to have
our simulations work properly
Change the reltol, vabstol, and iabstol to 1e-1, 1e-1, and
1e-3 in order to stop a problem of convergence from affecting the simulations.
Now we can test our DAC by applying different loads to the output and
simulating, the first being a resistive load of 10k.
From the simulation above we see that when attaching a 10k load, the DAC and
the 10k load became a voltage divider and half the output to 2.5V.
Now we’ll look at when the output has a capacitive load of 10pF.
This simulation tells us that when driving a capacitor of 10pF, the output
smoothes out, and it lags behind the input by about
70ns.
Now testing when the output is driving both the 10k and 10pF loads.
With the last simulation, adding both the resistor and capacitor causes the
output to smooth out, nearly halves the input voltage,
and it lags about 50ns from the input.
According to all the information from the simulations, we can conclude
that both the input and output are in-phase when only the output
is driven by a resistive load. Also, that it remains out-phase when a capacitive
load is present on the output.
3.
Switch resistance
If circuit was real and the switches were implemented with transistors, and the resistance on the switches wasn’t
small compared to R, then equivalent resistance of the entire DAC would not be R and we would need to recalculate the resistance of the DAC in order to
acquire
the correct output.
4. Back-up of Data
For
lab 2, the folder containing the lab2 library was downloaded to the desktop and
zipped.
The lab2 zip was then sent and archived via email.
