Lab 7 - EE 421L Fall 2020
   
Authored by Abraham Lopez on 11/1/20
Email: lopeza43@unlv.nevada.edu
 
   
Lab description
The purpose of this lab was to create, using buses and arrays, schematics for word inverters, muxes,
and high-speed adders. Then taking those schematics and testing them through simulations to see how
they operate. The lab also involved laying out an 8-bit full adder.
 
Pre-lab
The pre-lab involved backing up our previous lab work and then completing tutorial 5. To start off
we copied the library for tutorial 5 and renamed it tutorial 5. Then created a new cell view schematic
called ring_osc.

Next, creating the schematic for a ring oscillator using an inverter.

 
Symbol of oscillator

 
Layout of 31-stage oscillator

 
DRC and LVS of layout

   
Adding an initial condition of 0 for the simulation of the oscillator

 

 

 
Simulation results

 
Simulation of the ring oscillator


Simulation results with the extracted view

   

 
This ends the pre-lab.
 
Lab Procedures
1. Creating and simulating a 4-bit inverter

Creating a schematic for a 6u/6u inverter.

 
Making a symbol of the inverter then using it to make a 4-bit inverter schematic.

   
Symbol of the 4-bit inverter

   
Simulation schematic of the 4-bit inverter

   
Simulation results

Looking at the simulation results we see the effect that a capacitative load has on the output. Out<0> has no load and is very fast
when it comes the rise and fall times of the output. Out<1> has the largest load with 1 pF on the output and has the slowest raise and
fall times. We can conclude that the bigger the load on the output the larger the time delay for the capacitor to charge is.
 
2. Creating and simulating 8-bit NOR, NAND, Inverter, AND, and OR gates
   
Schematic of NOR gate

 
Symbol of NOR gate

 
Schematic of NAND gate

 
Symbol of NAND gate

   
Schematic of Inverter gate

   
Symbol of inverter gate

   
Schematic of AND gate

 
Symbol of AND gate

 
Schematic of OR gate

 
Symbol of OR gate

   
Schematic of 8-bit NAND gate

 
Symbol view of 8-bit NAND gate

 
Schematic of 8-bit NOR gate

 
Symbol of 8-bit NOR gate

 
Schematic of 8-bit inverter gate

 
Symbol of 8-bit inverter gate

   
Schematic of 8-bit AND gate

 
Symbol of 8-bit AND gate

   
Schematic of 8-bit OR gate

 
Symbol of 8-bit OR gate

   
Simulation of all 8-bit gates

   
Simulation results

   
3. Creating and simulating 2:1 MUX/DEMUX
 
Schematic of 2:1 MUX

 
Symbol of 2:1 MUX

   
Simulation of 2:1 MUX

 
Simulation results

The MUX works by when sending a 1 to S then the input A is outputted to Z. If S is 0, then Si is 1 then the input B
is outputted to Z.
   
Schematic of 2:1 MUX/DEMUX

 
Symbol of 2:1 MUX/DEMUX

 
Simulation of 2:1 MUX/DEMUX

   
Simulation results

The MUX/DEMUX works when S is 1 , then the input signal A propagates through A'. If S is 0, then the input signal A
propagates through B'.
 
4. Creating and simulating 2:1 MUX with a single select input
   
Schematic of 2:1 MUX with a single select input

   
Symbol of 2:1 MUX with a single select input

 
Simulation of 2:1 MUX with a single select input

 
Simulation results

   
5. Creating and simulating an 8-bit 2:1 MUX/DEMUX with single select input
 
Schematic of 8-bit 2:1 MUX/DEMUX with single select input

 
Symbol of 8-bit MUX/DEMUX with single select input
 
 
Simulation of 8-bit 2:1 MUX/DEMUX with single select input

 
Simulation results

 
6. Creating and simulating an 8-bit Full adder
 
First we start of by making the schematic of a full adder given by Fig. 12.20 in the CMOS book.

    
Symbol of full adder

   
Simulation of full adder

 
Simulation results

 
Layout of full adder

 
DRC and LVS of layout

   

 
Schematic of an 8-bit full adder

 
Symbol of an 8-bit full adder

 
Simulation of an 8-bit full adder

 
Simulation results

 
Layout of an 8-bit full adder

 

 

 

 
DRC and LVS of layout

 

   
7. Back of lab work

I zipped up a copy of lab 7 and sent it to myself via email.

 


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