EE 421L – Digital
IC Design Lab
Fall 2020
Labs
Lab
1 - Laboratory introduction,
generating/posting html lab reports, installing and using Cadence, due
September 2
Lab
2 - Design of a 10–bit digital–to–analog
converter (DAC), due September 9
Lab
3 - Layout of a 10–bit DAC, due September 16
Lab
4 - IV characteristics and layout of NMOS
and PMOS devices in ON's C5 process, due September 23
Lab
5 - Design, layout, and simulation of a
CMOS inverter, due October 7
Lab
6 - Design, layout, and simulation of a
CMOS NAND gate, XOR gate, and Full–Adder, due October 21
Lab
7 - Using buses and arrays in the design
of word inverters, muxes, and high–speed adders, due
November 4
Lab
8 - Generating a test chip layout for
submission to MOSIS for fabrication, due December 2
Project
– High Speed Digital Receiver