Email: alvara6@unlv.nevada.edu
October 21,
2020
Lab Description
·
Design,
layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder
Pre - Lab
- Back-up
all of your work from the lab and the course.
- Go
through Cadence
Tutorial 4 seen here.
- Read through the lab
in its entirety before starting to work on it
Backing up work from previous labs
Tutorial 4
NAND Schematic
and Symbol
Testing the
NAND symbol
Output of the
NAND schematic
Layout and
Extracted views of the NAND 2
LVS command
window showing that the netlists match. The following picture is when we click
on the “Compare FET parameters”.
When we run
the LVS now it will say that the netlists match, but that the FET parameters
are not the same. To eliminate this issue, we can either switch the
Length and
width in the schematic view to account for the layout view or we can change the
layout size of the FET to correspond with the schematic view.
Lab Tasks
- Draft the schematics of a
2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using
6u/0.6u MOSFETs (both NMOS and PMOS)
- Create layout
and symbol views for these gates showing that the cells DRC and LVS
without errors
- ensure that
your symbol views are the commonly used symbols (not boxes!) for these
gates with your initials in the middle of the symbol
- ensure all
layouts in this lab use standard cell frames that snap together
end-to-end for routing vdd! and gnd!
- use
a standard cell height taller than you need for these gates so
that it can be used for more complicated layouts in the future
- ensure gate
inputs, outputs, vdd!, and gnd! are all
routed on metal1
- Use cell names
that include your initials and the current year/semester, e.g.
NAND_jb_f19 (if it were fall 2019)
- Using Spectre simulate the logical operation of the gates
for all 4 possible inputs (00, 01, 10, and 11)
- comment on
how timing of the input pulses can cause glitches in the output of a
gate
- Your html lab
report should detail each of these efforts
- Below shows
(click for a larger image): 1) schematic of a 2-input NAND gate, 2)
schematic of a 2-input XOR gate, 3) simulation schematic, 4) example
pulse statement to generate a digital input, and 5) simulating the
operation of the gates for all 4 possible inputs.
- Using
these gates, draft the schematic of the full adder seen below
- Create a symbol for this full-adder (example)
- Simulate, using Spectre, the
operation of the full-adder using this symbol
- Layout
the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
- full-adder inputs and outputs can be on metal2 but not
metal3
Lab
NAND 2-
Schematic and Symbol
Note that for
the schematics we are supposed to use 6u/0.6u (both NMOS and PMOS)
Here are the
layout and extracted view of the NAND 2. Note that the layout/ extracted views
have the same length and width of the schematic eliminating the FET parameters
Error when we
LVS.
DRC with 0
errors and the netlists match for the LVS.
Testing the
NAND 2 gate that I have created. The following is the output window which is
showing that the NAND2 gate is working appropriately. Simulation was done using
Spectre
XOR 2 – Schematic
and Symbol
Note that for
the schematics we are supposed to use 6u/0.6u (both NMOS and PMOS)
Layout and
Extracted View
DRC with 0
errors and the netlists match for the LVS.
Testing the
XOR 2 gate that I have created. The following is the output window which is
showing that the XOR 2 gate is working appropriately. Simulation was done using
Spectre.
Here is an example
of a pulse statement to generate a digital input signal for the B input source of
the XOR2 sim up above.
Glitches are present
for the NAND and XOR sims because of the rise and fall times of the input
signal. The glitch is when the input of
the pulse is rising or falling so for that instant the MOSFETS are not on or
off. If the rise and fall times were even decreased more than this would make
the glitches even smaller and smaller.
Full Adder - Schematic
and Symbol
Testing the
FULL ADDER gate that I have created. The following is the output window which
is showing that the FULL ADDER gate is working appropriately.
Simulation
done using Spectre.
Layout and
Extracted View. For the layout of the full adder inputs and outputs can be on
metal2, but not metal 3.
DRC with 0
errors and the netlists match for the LVS.
Backing Up Work
As seen by the snips
above these were the steps that I used to back up my work. First, I found the
tutorial folder in my CMOSedu folder in the MobaXTerm.
After finding where
the folder was, I downloaded the folder to the desktop and later sent it to a
compressed zipped folder.
After making a ZIP
file I uploaded them to my google drive with the date in the
title. This should complete my backup process. This will be the
process I use in the future.
This concludes Lab 6.