Lab 3 - EE 421L 

Author: Armani Alvarez

Email: alvara6@unlv.nevada.edu

September 9, 2020

Lab Description

· Layout of a 10-bit digital-to-analog converter (DAC) 

Pre - Lab

• Back-up all of your previous work from the lab and the course.
• Finish Tutorial 1 seen here.

Here is the backed-up work from the previous labs and the beginning of today’s lab.

The next snips show me completing tutorial 1. We also had to complete tutorial 1 for a lecture homework problem. The snip below is showing how to calculate the resistor value.

The R sheet value is going to equal to 800 ohms / sheet. Next we have to select length and width values that are divisble by .15 micron and the result be a whole number if not when running the DRC

there will be errors.

This is the length and width that I have chosen to complete tutorial one, as well as lab 3. To edit these porperties, click on the rectangle that was drawn and hit bindkey Q and change the parameters.

R = 800 * ( 54 / 4.2 ) = 10.285K, which is very close to our desired value of 10K.

Here is the extracted view with the resistor value of 10.53K. When making a resistor value on candece a user will never get very accurate results, but as long as you are in the ten percent margin the user will be fine.

This is a picture of making a volatge divider out of three 10K n well resistors.

Lab Tasks

This lab will focus on the layout of the 10-bit DAC you designed and simulated in Lab 2

• Use the n-well to layout a 10k resistor as discussed in Tutorial 1 
• Discuss, in your lab report, how to select the width and length of the resistor by referencing the process information from MOSIS
• Use this n-well resistor in the layout of your DAC
• Discuss, in your lab report, how the width and length of the resistor are measured 
• Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked)
• All input and output Pins should be on metal 1
• DRC and LVS, with the extracted layout, your design (show the results in your lab report)
• Zip up your final design directory and place it in the lab3 directory, with a link on your lab report, so the grader can examine both the layout and schematic (and simulations)

· LAB 3 ZIP

Lab

This is a snip from lab 2 in where I had to test the DAC symbol that I had created. The symbol I created had the correct simulation.

These snips is how I made my symbol up above. First, I started making a volatge divider schematic and later I made a symbol. I added 10 symbols plus

another 10k resistor in order to make my Digital to Analog converter.

These are snips from my lab 3 in which I am recreating the symbols above, but instead I made the symbol out of n well resistors. To accomplish this task I had to connect 31 10K resistors together

to make a DAC. What I mean by connecting the resistors together in this lab is that we are supposed to ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked). In the first picture it is a zoomed-out view showing that I had to place 31 resistors. The next three snips are showing how I connected the resistors in an more in depth view, such as B9-B0, Vout, GND! were connected. Another thing to be noted is that all input and outputs pins are laid out on layer metal 1.

In these next set of snips I am showing the LVS menu and the files that I have selected. The next snip is showing how the LVS worked and how the netlists match. One thing Dr. Baker always emphasizes is that we are using the lastest set of DIVA rules that you can see below. The last snip in this set is showing when I run a DRC that there are zero errors!

Backing Up Work

As seen by the snips above these were the steps that I used to back up my work. First, I found the tutorial folder in my CMOSedu folder in the MobaXTerm.

After finding where the folder was, I downloaded the folder to the desktop and later sent it to a compressed zipped folder.

After making a ZIP file I uploaded them to my google drive with the date in the title.  This should complete my backup process. This will be the process I use in the future.

This concludes Lab 3.

Return to Lab Reports