Lab 4 - EE 421L 

Author: Armani Alvarez

Email: alvara6@unlv.nevada.edu

September 16, 2020

Lab Description

IV characteristics and layout of NMOS and PMOS devices in ON's C5 process

Pre - Lab

• Back-up all of your work from the lab and the course.  
• Read through this lab before starting it.
• Go through Tutorial 2 seen here. 
• In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V. 

Backing up all of my work that I have completed up to this point.

In the following snips I am showing how I completed tutorial 2.

NMOS – showing the schematic and the symbol.

Testing the symbol to see the results.

Here is the layout view as well as the extracted view of the NMOS transistor.

I ran an LVS and the snip shows that the netlists match.

Showing the results of the sim and showing the netlist output to prove that the extracted view is the one being simulated.

PMOS – Layout view of the PMOS transistors.

Testing the symbol. This is the expected output to be received.

Ran the LVS to prove that the netlist match.

Showing the results of the sim and showing the netlist output to prove that the extracted view is the one being simulated.

Lab Tasks

• Generate 4 schematics and simulations (see the examples in the Ch6_IC61 library, but note that for the PMOS body should be at vdd! instead of gnd!):
• A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
• A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again, use a 6u/600n width-to-length ratio.
• A schematic for simulating ID v. VSD (notes VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
• A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.  
• Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small). 
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout. 
• Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads. 
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout. 
• Some examples are seen below (click for a larger view). 
• They are, in order: 1) probe pad layout, 2) probe pad schematic, 3) probe pad symbol, 4) schematic of the MOSFET with probe pads, 5) corresponding symbol view, 6) corresponding layout (which is DRCed and LVSed), 6) zoomed in view of the layout, and finally 7) simulation schematic for ID v VSD for varying VSG (which is not used for an LVS since there is no way to lay out a battery).  
• These cells are found in lab4.zip

Lab

Making the NMOS schematic and symbols. 6u/600n

Making the PMOS schematic and symbols. 12u/600n

A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps.

A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps.

A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps.

A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps.

Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads. Here a view of the layout as well as a zoomed in snip to show the connections made to the probe pads.

Snip showing the DRC passing and the LVS matching.

Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads. Here a view of the layout as well as a zoomed in snip to show the connections made to the probe pads.

Snip showing the DRC passing and the LVS matching.

Backing Up Work

As seen by the snips above these were the steps that I used to back up my work. First, I found the tutorial folder in my CMOSedu folder in the MobaXTerm.

After finding where the folder was, I downloaded the folder to the desktop and later sent it to a compressed zipped folder.

After making a ZIP file I uploaded them to my google drive with the date in the title.  This should complete my backup process. This will be the process I use in the future.

This concludes Lab 4.

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