Lab 2 - EE 421L

Author: Armani Alvarez

September 2, 2020

Lab description

· This lab covers the design of a 10-bit digital-to-analog (DAC) converter

Pre – Lab

Prior to coming to lab make sure you understand how the input voltage, Vin, is related to B [9:0] and Vout (the quiz may ask a question about this).
In your lab report: 1) provide narrative of the steps seen above, 2) provide, and discuss, simulation results different from the above to illustrate your understanding of the ADC and DAC, 3) explain how you determine the least significant bit (LSB, the minimum voltage change on the ADC's input to see a change in the digital code B [9:0]) of the converter. Use simulations to support your understanding.
Backup your webpages and design directory.

How is Vin related to B [9:0] and Vout?

· Vin is related to B [9:0] by 10-bit representation of the source, which is the Vin value. B [9:0] represents a different digit of the 10-bit binary representation, with B9 being the most significant bit and B0 being the least significant bit. The ADC block receives an analog value which it converts into binary value. From here this binary code is the output of the ADC and this binary code is received by the DAC. Later the DAC converts the binary code from the input and outputs it as an analog waveform. The resolution is based on the numbers of bits we are using. The greater the number of bits the more accurate representation we will get of the input value Vin.

Pre- Lab narrative

First, I downloaded the lab2.zip to my desktop, then I uploaded to the design directory to cds.lib in MobaXterm.

Here I am showing that lab 2 folder shows in my CMOSedu folder in MobaXterm.

The snip above shows the text that I added into cds.lib so that Cadence would recognize this file.

At this point I open up Cadence by using ‘virtuoso &”.

To open the schematic above use the following steps.

· Open “lab2” schematic

· Open “sim_ideal_ADC_DAC” cell

· Open schematic view

Then we launch “ADE L” and then we load the last state and this is what we should see.

At this point hit the green play button.

This is the result that we receive. I got this aesthetically pleasing schematic by right clicking graph properties

and changing the background color to white. Next, I right clicked either vin or vout and change the color, width, and style of the lines.

I did these steps to help readers to easily read my graphs.

Graph #1

DC Offset: 2.5V

Amplitude: 2.5V

Graph #2

DC Offset: 2.5V

Amplitude: 0.01V

Here I am confirming the values from Graph #2. 2.505 - 2.5 = .005 which is 5mV which is around the value of 4.883mV that I have calculated

in the figure down below.

How to determine the Least Significant Bit

Lab Tasks

· Design a 10-bit DAC using an n-well resistor of 10k

· How to determine the output resistance of the DAC (answer: R) by combining resistors

· Delay, driving a load

· How to create a symbol view for your design with the exact same footprint as the Ideal_10-bit_DAC symbol

· Simulations to verify correct design functionality

Lab

First, we created a voltage divider by having two 10K resistors in series and another 10K resistor in parallel to those. After laying down the resistors then we added three

pins which were IN, OUT, and CONN. Once this was completed we click “create”, ‘cell view’, “from cell view”, and create a symbol of the voltage divider schematic.

Schematic

Symbol for schematic of voltage divider

The next step for this lab is to have 10 of the symbols of the voltage divides that we made and connect them with wires and add a 10K resistor at the bottom.

From this point we make another symbol for the 10 symbols and make another symbol by clicking “create”, ‘cell view’, “from cell view”, and create a symbol of the voltage divider schematic.

At this point we have multiple things in our hierarchy starting off with the voltage divider, the symbol for the voltage divider, the 10 symbols of the voltage dividers, and now the symbol for the 10-bit DAC.

More schematics and symbols

Hand Calculations

For finding the resistance of a 10-bit DAC. First, we start off at the bottom of the circuit. We should know from earlier circuits classes 2R||2R=R. From this point we continue minimizing the circuit.

To find the time delay we have to realize that this circuit is basically an RC circuit. Since we can conclude that this is an RC circuit that we can use the formula td = (.7) (R) (C).

For this circuit we should get td = (.7) (10k) (10p) = 70ns.

In the snip below, I am testing my block to see if I am getting the same results as my hand calculations.

As shown by the waveforms below my hand calculations and waveforms math up meaning that the delay is 70ns.

No Load DAC Simulation

For this simulation we are testing the DAC that we created. When I simulate this, I am simulating without load. As you can see the output waveform is the same output waveform that we received

in the prelab, which was an ideal DAC.

10k Resistive Load DAC Simulation

In this simulation we are simulated the ADC to DAC with a 10K resistive load. In turn we know that the DAC is 10K and now is connected in series with another 10K. By doing this it acts like a voltage divider cutting down the voltage.

10pF Capacitive Load DAC Simulation

When we simulate with the 10pF capacitor we can see from the waveform that the output is very smooth compared to the no load and resistive load circuits.

Another observation that we can see from the waveform is that Input leads and the Output lags by around 70ns.

R||C (Resistive and Capacitive) Load DAC Simulation

From this circuit we can see that the output voltage is half of the input voltage and smooth compared to the no load or resistive load circuit.

Conclusions about these simulations

What I can conclude about these simulations is that both the no load and resistive load circuits are in phase. When we add a capacitor to the DAC then we get a smooth output voltage along with a delay. When we have both a resistor and capacitor on the load for the DAC then we also have a delay but not as long as the capacitive only delay and this is because of the additional resistor of 10K coming into play.

Question

In a real circuit the switches seen above (the outputs of the ADC) are implemented with transistors (MOSFETs).

Discuss what happens if the resistance of the switches isn't small compared to R.

If the resistance of the switches is not small compared to R the REQ of the DAC would be different. We would have to calculate a different Req because the series resistance of each the bits would be higher causing a REQ that is actually greater than R.

Possible Problems Encountered

If you have simulation convergence problems you can force the simulation to converge by going to, in the ADE, Simulation -> Options -> Analog

Set the values as seen below

relative tolerance, reltol, of 10% (= 1e-1)
voltage absolute tolerance, vabstol, of 100 mV (= 1e-1)
current absolute tolerance, iabstol, of 1 mA (= 1e-3)

Backing Up Work

As seen by the snips above these were the steps that I used to back up my work. First, I found the tutorial folder in my CMOSedu folder in the MobaXTerm.

After finding where the folder was, I downloaded the folder to the desktop and later sent it to a compressed zipped folder.

After making a ZIP file I uploaded them to my google drive with the date in the title. This should complete my backup process. This will be the process I use in the future.

This concludes Lab 2.

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