Lab 7 - EE 421L
Email: alvara6@unlv.nevada.edu
November 4,
2020
Lab Description
Using buses and arrays in the design of word
inverters, muxes, and high-speed adders
Pre - Lab
- Back-up
all of your work from the lab and the course.
- Go
through Tutorial 5 seen here.
Going through tutorial 5
Lab Tasks
·
Create schematics and
symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR
gates.
Provide a few simulation examples using these gates.
·
This is the schematic of
a 2-to-1 DEMUX/MUX (and the symbol).
Simulate the operation of this circuit using Spectre
and explain how it works.
·
Make sure to show, using
simulations, how the circuit can be used for both multiplexing and
de-multiplexing.
·
Create an 8-bit wide word 2-to-1 DEMUX/MUX
schematic and symbol.
Include an inverter in your design so the cell only needs one
select input, S (the complement, Si, is generated using an inverter).
Use simulations to verify the operation of your design.
·
Finally, draft the schematic of the full-adder
seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
Create an adder symbol for this circuit (see the symbol used
in lab6).
Use this symbol to draft an 8-bit adder schematic and symbol.
For how to label the bus so the carry out of one full-adder
goes to the carry in of another full-adder review the ring oscillator schematic
discussed in Cadence Tutorial 5.
Simulate the operation of your 8-bit adder.
·
Lay out this 8-bit adder cell (*note* that this
is the only layout required in this lab).
Show that your layout DRCs and LVSs correctly.
·
This ends lab 7. We've covered all of the
basic building blocks used in an ALU.
Lab
4 bit INVERTER
8 bit I/O
Array of INVERTER
8 bit I/O
Array of NAND
8 bit I/O
Array of NOR
8 bit I/O
Array of AND
8 bit I/O
Array of OR
Simulation
A and B inputs
act as the inputs of a truth table. Example A is = 0011 and B is = 0101. All
the outputs are what we expected for these digital logic gates.
2:1 MUX
Simulation
When the S is
high, then all of the outputs following the A input. If S is low, then all of
the outputs follow the B input.
2:1 Mux/Demux
Simulation
For the mux
when the S is high, then all of the outputs following the A input. If S is low,
then all of the outputs follow the B input.
For the demux when the S is high, the input signal Y only goes to
C. If the S is low, then input signal goes to D.
2:1 MUX WITH SINGLE SELECT INPUT
One can
connect an inverter to the S input, replacing 2 parts which are S and Si.
Tying the
output of the inverter to the output allows to have a single select input.
DESIGN AN SIMULATION OF 8 BIT MUX
Simulation
When the S is
high, then all of the outputs following the A input. If S is low, then all of
the outputs follow the B input.
AOI FULL ADDER
SCHEMATIC and
AOI FULL ADDER SYMBOL. The schematic of the AOI Full Adder can be found on
figure 12.20 found in the CMOS book.
8 BIT AOI FULL ADDER
Simulation
Two 8 bit numbers were added to produce 8 bit sum with no carry
in.
(binary) (decimal)
B = 10000001 = 129
A = 00000111 = 7
S = 10001000 = 136
Layout of a
single AOI FULL ADDER
EXTRACTED
DRC AND LVS.
The DRC and LVS were completed successfully.
Layout of AOI 8 BIT FULL ADDER ZOOMED IN
LAYOUT VIEW
ZOOMED OUT
EXTRCATED VIEW
ZOOMED OUT
DRC AND LVS.
The DRC and LVS were completed successfully.
Backing Up Work
As seen by the snips above these were the steps that I used to
back up my work. First, I found the tutorial folder in my CMOSedu folder in the MobaXTerm.
After finding where the folder was, I downloaded the folder to the
desktop and later sent it to a compressed zipped folder.
After making a ZIP file I uploaded them to my google drive with
the date in the title. This should complete my backup process. This
will be the process I use in the future.
This concludes Lab 7.