EE 421L - Digital Integrated Circuit Design
Lab
Author: Abraham Lopez
Email: lopeza43@unlv.nevada.edu
Fall 2020
Laboratory Reports
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Laboratory |
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Laboratory introduction, generating/posting html lab reports, installing and using Cadence |
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Design of a 10–bit digital–to–analog converter (DAC) |
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Layout of a 10–bit DAC |
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IV characteristics and layout of NMOS and PMOS devices in ON's C5 process |
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Design, layout, and simulation of a CMOS inverter |
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Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder |
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Using buses and arrays in the design of word inverters, muxes, and high–speed adders |
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Generating a test chip layout for submission to MOSIS for fabrication |
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