EE 421L: Digital Integrated Circuit Design Lab

Dominic Hryciuk 
hryciuk@unlv.nevada.edu

Fall 2017

Project - 9-bit Even Parity Checker with 8-bit data word

Lab8 - Generating a test chip layout for submission to MOSIS for fabrication: Chip6_f17.

Lab7 - Buses and arrays in the design of word inverters, muxes, and high–speed adders

Lab6 - Design, layout and simulation of CMOS NAND gate, XOR gate and Full Adder

Lab 5 - Design of CMOS inverter

Lab 4 - IV characteristics of NMOS/PMOS

Lab 3 - Layout of 10-bit DAC

Lab 2 - Design of 10-bit DAC

Lab 1 - Lab introduction

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