Lab 7 - ECE 421L
When using busses, the naming of the net becomes very important. To single out a connection, you must connect a wire with the name corresponding to the connection to be measured. This is done in the test circuit to measure the responses of different capacitive loads.
A higher capacitive load increases the rise and fall times; a large capacitor is much slower with charging and discharging. Consequently, the delay before the output reaches steady state is longer with larger capacitors.
8-bit input/output arrays are created for a variety of digital logic devices: NAND, NOT, AND, and OR gates. To test the operation of each device, a general test circuit is used as shown below with an AND gate.
In this array of connections, each gate has the same two inputs coming in, which change to show operation of the AND gate. The simulation shows 8 outputs, each corresponding to an instantiated AND gate.
Below is the testing of an 8-bit NAND gate.
Below is the testing of an 8-bit NOR gate.
Below is the testing of an 8-bit OR gate. The schematic is omitted but is the same format as above.
The operation of a 2-to-1 MUX/DEMUX is analyzed. A multiplexer takes many inputs and selects only one, while a de-multiplexer takes one input and chooses what output to show it. Both devices select which signal to choose based on a seperate control signal. A MUX/DEMUX is a device which is capable of performing both these operations depending on demand.
First, MUX operation is tested. A MUX selects an output based on the equation:
With preset voltage levels at each input, it is easy to see when an input is selected to be at output. A is at VDD, while B is grounded. Operation follows the equation.
DEMUX operation is tested next. A DEMUX device is made by modifying the inputs of the same circuit used above; it is no different aside from where the signals are coming from. The selector control signal will determine what path the signal goes down: A on low, B on high.
Using the full adder design from a previous lab, an 8-bit full adder is designed. Like the other designs in this lab, it is created using an array of instances. However, the connections for input and output are a little different for proper operation. For an 8-bit full adder, the carry-out of the previous adder is used as the carry-in for the next one. This must be accounted for through the naming of the busses connected to each pin.
Testing of the 8-bit full adder can be done with a sample input. Each input is predetermined and the output is observed. In this case, 01010101 and 01011001 are added (85 + 89 = 174 = 10101110).
When Cin is changed to 1, the result increases by 1 to 175 (10101111) as expected.
