Lab 8 - EE 421L

Chip6_f17

Dominic Hryciuk - hryciuk@unlv.nevada.edu
Andy Sam - sama1@unlv.nevada.edu
Prachi Patel - patelp3@unlv.nevada.edu

zipped file: Chip6_f17
PRELAB:
Updated Google Drive and saved all the lab work.
Followed tutorial 6 and the completed designs are used in the lab below.

LAB
For our project, we built a parity checker that ouputs 0 for odd number of high inputs and 1 for even number of high inputs. For this lab, we will generate a test chip layout for the project.

Testing Chip: To test the chip, use the pin diagram given below and insert the chip into a breadboard. Ground is common for all circuits at pin <20> but Vdd in not common and each circuit is powered at a different pin. For example, to test the voltage divider, supply 5V at pin<18>  and ground pin<20>. The voltage measured at pin<19> should be about 1.43V. To test the inverter, supply a voltage at pin<16> and connect Vdd at pin<15>. The output voltage measured at pin<17> will be opposite of pin<16>.

For parity checker, supply voltages (varying to confirm results) to pin<21-29> and Vdd to pin<31>. The voltage measured at pin<30> is the resulting check that was simulated in Project.

Pin diagram

z                 
Complete Pin Table

Pin
 Device
 Connection
 Pin
 Device
 Connection
 Pin
 Device
 Connection
 Pin
 Device
 Connection
1

13
 Ring Oscillator
 Vdd
 25
 Parity Checker D4
 37

2
 NAND
 C
 14
 Ring Oscillator
 out
 26
 Parity Checker D5
 38

3
 NAND
 B
 15
 Inverter
 Vdd
 27
 Parity Checker D6
 39

4
 NAND
 A
 16
 Inverter
 A
 28
 Parity Checker D7
 40

5
 NAND
 Vdd
 17
 Inverter
 Ai
 29
 Parity Checker Parity


6
 PMOS
 Gate - G
 18
 Voltage Divider
 Vin
 30
 Parity Checker check


7
 PMOS
 Drain - D
 19
 Voltage Divider
 Vout
 31
 Parity Checker Vdd


8
 PMOS
 Body - B
 20
 Common
 GND!
 32
 NOR
 A


9
 PMOS
 Source - S
 21
 Parity Checker
 D0
 33
 NOR
 B


10
 NMOS
 Drain - D
 22
 Parity Checker D1
 34
 NOR
 C


11
 NMOS
 Source - S
 23
 Parity Checker D2
 35
 NOR
 Vdd


12
 NMOS
 Gate - G
 24
 Parity Checker D3
 36








CHIP
Schematic
 f
Layout
 s
Extracted
 s
DRC
 a
LVS
 z


PARITY CHECKER
Pin
 Device Connection
20
 Common
 GND!
21
 Parity Checker
 Input - D0
22
 Parity Checker
 Input - D1
23
 Parity Checker Input - D2
24
 Parity Checker Input - D3
25
 Parity Checker Input - D4
26
 Parity Checker Input - D5
27
 Parity Checker Input - D6
28
 Parity Checker Input - D7
29
 Parity Checker Input - Parity
30
 Parity Checker Output - Check
31
 Parity Checker Input - Vdd
x x


NAND
Pin
 Device
 Connection
2
 NAND
 Output - C
3
 NAND
 Input - B
4
 NAND
 Input - A
5
 NAND
 Input -Vdd
20
 NAND
 Common - GND!
d x


NOR
Pin
 Device
 Connection
32
 NOR
 Input -A
33
 NOR
 Input - B
34
 NOR
 Output - C
35
 NOR
 Input - Vdd
20
 NOR
 Common - GND!
r s


RING OSCILLATOR
Pin
 Device
 Connection
13
 Ring Oscillator
 Input - Vdd
14
 Ring Oscillator
 Output - out
20
 Ring Oscillator
 Common - GND!
2 3


INVERTER
Pin
 Device
 Connection
15
 Inverter
 Input - Vdd
16
 Inverter
 Input - A
17
 Inverter
 Output - Ai
4 5


PMOS
Pin
 Device
 Connection
6
 PMOS
 Gate - G
7
 PMOS
 Drain - D
8
 PMOS
 Body - B
9
 PMOS
 Source - S
x e


NMOS
Pin
 Device
 Connection
10
 NMOS
 Drain - D
11
 NMOS
 Source - S
12
 NMOS
 Gate - G
20
 NMOS
 Body - B (Common - GND!)
1 2


VOLTAGE DIVIDER
Pin
 Device
 Connection
18
 Voltage Divider (25K)
 Input - Vin
19
 Voltage Divider
 Output - Vout
20
 Voltage Divider (10K)
 Common - GND!
Testing 25K Resistor: To test 25K resistor by itself, connect voltage supply to pin<18> and connect the gnd to pin<19>. Leave pin<20> unconnected.
Testing 10K Resistor: To test 10K resistor by itseld, connect voltage supply to pin<19> and gnd to pin<20>.

3 3


Additional pictures for schematic, symbol, layout, extracted

END


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