Lab 4 - ECE 421L
To observe ID vs. VDS characteristics, an NMOS device is tested with a varying VGS from 0 to 5 V, in 1 V steps, and a varying VDS from 0 to 5V in 1mV steps. The NMOS has a 6u/600n width-to-length ratio.
Normally, VGS would have to be constant while a sweep is performed across VDS, meaning there would have to be 5 separate tests to observe the relationship. However, this can be condensed by using parametric analysis. The simulation is performed for 5 different test points of VGS at the same time. For a larger VGS, the saturation voltage is higher and the linear region of increase lasts longer.
A sweep is performed on VGS; unlike the previous test, VDS is held constant. Thus, only one simulation is needed and parametric analysis has no use. This simulation tells us that there is a certain threshold voltage on the device before a signal is let through. The larger this difference, the more of the signal is passed.
To observe ID vs. VSD characteristics, a PMOS device is tested by allowing VGS to vary from 0 to 5V in 1V steps, while VSD varies from 0 to 5V in 1mV steps. A width-to-length ratio of 12u/600n is used for the PMOS device.
