Digital Integrated Circuit Design - ECE 421L
University of Nevada, Las Vegas
Fall 2023
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Taught by Professor: R. Jacob Baker, PhD, PE
Authored
by Dara Wells
Email: wellsd5@unlv.nevada.edu
"This thing all things devours:
Birds, beasts, trees, flowers;
Gnaws iron, bites steel;
Slays kings, ruins towns,
And beats high mountains
down."
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Labs:
Lab 1: Cadence Introduction
Lab 2: Design of a 10-bit DAC
Lab 3: Layout of a 10-bit DAC
Lab 4: IV Characteristics and Layout of NMOS and PMOS Devices
Lab 5: Design, layout, and simulation of a CMOS inverter
Lab 6: Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder
Lab 7: Using Buses and Arrays in the design of word inverters, muxes, and high-speed adders
Lab 8: Generating a test chip layout for fabrication
Final Project: Non-inverting Buffer Circuit
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Riddle Answer: time
Whatever you do, don't click here.
Dawg with the butter...