Lab 5 - ECE 421L
Design, Layout, and Simulation of a CMOS Inverter
The prelab required us to complete Tutorial 3 which started with the following questions.
1: What does the Bindkey q do?
It opens an object for editing
2: Which two Cell Views are used when doing an LVS?
Schematic and Layout
3: What is the difference between the nmos and nmos4 schematic cells?
Nmos4 has a body connection whereas nmos does not
4: How do you select the MOSFET models in the ADE window? What does ADE stand for?
/$HOME /ncsu-cdk-1.6.0.beta/models/spectre/standalone/ami06N.m or ami06P.m
Analog Design Environment
5: What is the difference between moving and stretching?
Moving will move the entire object, stretching will change the dimensions of the object depending on where you select
6: How do you layout a rectangle on the metal1 layer?
First you select metal1 on the layer window on the left-hand side, then you press ‘r’ to select a rectangle, then you click for one corner of the rectangle and move your mouse to draw the rectangle, clicking again when you are finished.
7: What does the ! indicate at the end of gnd! And vdd!
It indicates that it is a global variable.
8: What do the acronyms LSW and CIW stand for?
LSW - Layer Selection Window
CIW - Command Interpreter Window
9: How is the ruler used? Cleared?
Press ‘k’ to use the ruler.
Press ‘shift- k’ to clear the ruler.
The tutorial had us go through creating an inverter and running simulations on it.
First, we created the schematic of the inverter as seen below:
Then we generated a symbol for our schematic:
Next, we created a layout for the inverter:
After we DRC our layout to verify everything is designed correctly:
We extract our layout so that we can run an LVS:
Then we use our inverter in a circuit:
Next, we run a simulation for the circuit with no incoming voltage and get the following output:
Then, we run the simulation with a voltage:
Next, we run the simulation with the extracted, which gives us the same plot as above, here is the proof of the sim running the extracted:
Lab:
First, we created a 12u/6u inverter:
Then we created the symbol for the inverter:
Next, we created a layout of the inverter:
After we created the layout, we created an extracted view and then ran LVS to verify:
Next, we created our 48u/4u inverter:
Then, we created a symbol for the inverter:
After that, we created a layout of the inverter:
Then, same as before, we extracted the layout and then ran LVS to verify:
The next parts of the lab had us create circuits to simulate using the inverters we created. First was the 12u/6u inverter for which the schematic of the circuit is as follows:
With this circuit, we ran a spectre simulation at 100fF, 1pF, 10pF, and 100pF, which I did using a parametric analysis sweep:
Next, we ran the simulation again using UltraSim instead of spectre:
Then we used the same circuit, but used the 48u/4u inverter we made:
First we ran the simulations using spectre at 100fF, 1pF, 10pF, and 100pF:
Then we ran the same simulations through UltraSim:
From the simulations, we can see that the higher the capacitance on the load, the slower the transition for the output. The 48u/4u inverter had a faster transition because with the increased size, the resistance decreased.
The
UltraSim simulations actually took longer to run than the spectre
simulations even though it is supposed to be faster with decreased
accuracy.
A copy of my Cadence files can be found here.
I backed-up my files as seen below:
