EE 421L Digital Integrated Design Laboratory

Authored by Martin Mercado

mercam13@unlv.nevada.edu

Professor: R. Jacob Baker,  PhD, PE

  

Labs:

Lab 1Laboratory introduction, generating/posting html lab reports, installing and using Cadence

Lab 2: Design of a 10–bit digital–to–analog converter (DAC)
Lab 3: Layout of a 10–bit DAC
Lab 4: IV characteristics and layout of NMOS and PMOS devices in ON's C5 process
Lab 5: Design, layout, and simulation of a CMOS inverter

Lab 6Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder

Lab 7Using buses and arrays in the design of word inverters, muxes, and high–speed adders

Lab 8Generating a test chip layout for fabrication

Lab Project: Design a non-inverting buffer circuit that presents less than 100 fF input capacitance to

on-chip logic and that can drive up to a 1 pF load with output voltages greater than 7V (an output logic 0 is near ground
and an output logic 1 is greater than 7V). Assume VDD is between 4.5V and 5.5V, a valid input logic 0 is 1V or less, a valid
input logic 1 is 3V or more. Show that your design works with varying load capacitance from 0 to 1 pF. Assume the slowest
transition time allowed is 4 ns.

 

Return to EE421 Labs