| Laboratory | Title | Due Date |
| Lab 1 | Laboratory introduction, generating/posting html lab reports, installing and using Cadence | 09/04/19 |
| Lab 2 | Design of a 10–bit digital–to–analog converter (DAC) | 09/11/19 |
| Lab 3 | Layout of a 10–bit DAC | 09/18/19 |
| Lab 4 | IV characteristics and layout of NMOS and PMOS devices in ON's C5 process | 09/25/19 |
| Lab 5 | Design, layout, and simulation of a CMOS inverter | 10/09/19 |
| Lab 6 | Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder | 10/23/19 |
| Lab 7 | Using buses and arrays in the design of word inverters, muxes, and high-speed adders | 11/06/19 |
| Lab 8 | Generating a test chip layout for submission to MOSIS for fabrication | 12/04/19 |
| Final Project | Design a circuit that takes a 9-11 MHz clock signal and generates a 36-44 MHz clock signal | 11/20/19 |