Lab 3: EE 421L

Layout of a 10-bit DAC
                     

Authored by: Kaylee Spencer

Email: spenck3@unlv.nevada.edu

Due: 09/18/2019

                     

Lab Description: This lab will focus on the layout of the 10-bit DAC we designed in the previous lab. 

                     

Prelab

                     

                     
We first needed to back up all of our previous work from the lab. I added it to my Google Drive to have all my lab work in one place. Then, we finished creating our 10-bit DAC layout from Tutorial 1.
                     

                     
Lab
Part 1
                   
I started by opening MobaXterm and then Virtuoso. When the Library Manager opens, I went to File -> New -> Cellview -> Type and selected "layout" in the drop box. I then used the n-well to create the layout of a 10k resistor, which is explained in Tutorial 1. When selecting the width and length of the resistor, we look at the C5 process parameters. Lambda is equal to 0.30um, which would cause the minimum width of the n-well to be 3.6 microns. We then find the length by using the equation below and plugging in the values we have for R, Sheet Resistsnce and W. After doing so, I got 75 microns.
                     

                     
Part 2
                     

                     
Next, we used the n-well resistor we created in the layout of our 10-bit DAC. Above is the 10k n-well resistor. Below is a close up view of the extracted 10-bit DAC layout. To create the 10-bit DAC layout, we copy and pasted 9 R_div components. Then we stacked them in parallel so they have the same x-position, but varying y-positions.
                     

                  
Then all we needed to do after that is verify the DRC and LVS for our design with the extracted layout.
                     
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