Lab 4: EE 421L

IV characteristics and layout of NMOS and PMOS devices in ON’s C5 process
                     

Authored by: Kaylee Spencer

Email: spenck3@unlv.nevada.edu

Due: 09/25/2019

                     

Lab Description: In this lab, we will be generating schematics and simulations for ID vs. VDS, ID vs. VGS, ID vs. VSD and ID vs. VSG. We will also be creating a layout for a 6u/0.6u NMOS device and a layout for a 12u/0.6u PMOS device. 

                     

Prelab

                     

First, we’re required to back up our work from the lab and the course, per usual. Then we needed to go through Tutorial 2, shown here. Below are some images I took while going through Tutorial 2.

                     

Part 1: NMOS

                     

                     

(values for the width and length)

                     

                     
For the NMOS, we needed to set the width to 6u and the length to 600n. Then create the schematic (above). We then create the schematic into a symbol and insert the symbol in the second schematic shown below.
                     

                     
(NMOS symbol)
                     

                     
(schematic with NMOS symbol used)
                     

                     
The graph I got from running the parametric analysis with the parameters specified in Tutorial 2 is shown above.
                     
Part 2: PMOS
                     
We then follow the same steps from creating the NMOS to create the PMOS. However, we do have different parameters the width, which is set to 12u and the length remains the same at 600n. Below are images for the first schematic, the PMOS symbol, the second schematic and final graph.
                     

                     
(schematic)
                     

                     
(PMOS  symbol)
                     

                     
(schematic with PMOS symbol used)
                     

                     
(graph)
                     

Lab

Part 1
                     
We are required to generate 4 schematics and simulations for the following…
                     
•    ID vs. VDS
                     
We first needed to create a schematic to simulate ID vs. VDS of an NMOS device for VGS varying from 0V to 5V in 1V steps while VDS varies from 0 to 5V in 1mV steps. We used 6u for the width and 600n for the length. We simply used the NMOS symbol we created in the prelab and placed it in the schematic below.
                     
 
                     
(schematic)
                     
 
                     
(width and length)
                     

                     
Above is the graph we get when we run the parametric analysis with variable VGS, value = 0, range type from 0 to 5 and linear steps with a step size of 1.

•    ID vs. VGS

We then needed to create a schematic to simulate ID vs. VGS of an NMOS device for VDS = 100mV where VGS varies from 0V to 2V in 1mV steps. We used the same width and length as the previous schematic. Again, we used the NMOS symbol we created in the prelab and placed it in the schematic below.
                     

                     

                     
When we run this schematic, we simply run it as a DC analysis and not parametric analysis like the previous schematic. Below is the graph I got after running it.
                     

                     
•    ID vs. VSD
                     
Next we needed to create a schematic to simulate ID vs. VSD of a PMOS device for VSG varying from 0V to 5V in 1V steps while VDS varies from 0 to 5V in 1mV steps. We used 12u for the width and 600n for the length. We simply used the PMOS symbol we created in the prelab and placed it in the schematic below.
                     

                     

                     
(width and length)
                     

                     
Above is the graph we get when we run the parametric analysis with variable VGS, value = 0, range type from 0 to 5 and linear steps with a step size of 1.
                     
•    ID vs. VSG
                     
Finally, we needed to create a schematic to simulate ID vs. VSG of a PMOS device for VSD = 100mV where VSG varies from 0V to 2V in 1mV steps. We used the same width and length as the previous schematic. Again, we used the PMOS symbol we created in the prelab and placed it in the schematic below.
                     

                     

                     
(width and length)
                     
When we run this schematic, we simply run it as a DC analysis and not parametric analysis like the previous schematic. Below is the graph I got after running it.
                     

                  
Part 2
                     
In order to create an NMOS, and PMOS, device, we first need to create a probe pad. A probe pad is created by laying a layer of glass and a layer of metal3. Below is my probe pad schematic, symbol and layout.
                     

                     

                    
   
                
6u/0.6u NMOS device


                     
(NMOS device schematic)
                     
We then needed to create an NMOS device with a width of 6u and a length of 0.6u. We started with instantiating a NMOS transistor, which is shown below.
                     

                     
After that, I created the layout below by connecting all 4 MOSFET terminals to probe pads using the correct vias for poly to metal 1, metal 1 to metal 2 and metal 2 to metal 3.
                     

                     
Below are two other zoomed in pictures of my layout.
                     

                     

                     
Finally, we DRC our layout and LVS our schematic.
                     

                     

                     
Part 3
                     
12u/0.6u PMOS device
                     

                     
(PMOS device schematic)
                     
Then we needed to create an PMOS device with a width of 12u and a length of 0.6u. We started with instantiating a NMOS transistor, which is shown below.
                     

                     
Similar to the NMOS, I created a layout by connecting all 4 MOSFET terminals to probe pads using the correct vias, which is shown below along with the zoomed in pictures.
                     

                     

                     

                     
Finally, we DRC our layout and LVS our schematic.
                     

                     

                     
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