Lab 6: EE 421L
Design, layout, and simulation of a CMOS NAND
gate, XOR gate, and Full-Adder
Authored by: Kaylee Spencer
Email: spenck3@unlv.nevada.edu
Due: 10/23/2019
Lab Description: This lab is meant to teach us how to, layout, and simulate a CMOS NAND gate, a XOR gate, and a Full-Adder.
Prelab
Part 1
For the prelab, we needed to go through Tutorial 4. Below I have added images from the tutorial.
Above is the NAND gate schematic as well as the symbol I created.
I then added the symbol into the schematic above in order to obtain the graph below, which shows the input (red) vs. the output (blue).
Finally, I created a layout of my NAND gate, ran a DRC, extracted the layout and then ran a LVS.
Lab
Part 1
NAND gate
We first needed to draft a schematic of a 2-input NAND gate using 6u/0.6u NMOS and PMOS MOSFETs and create a layout. The first part of the lab was done in Tutorial 4. However, I modified the layout a little.
Schematic:
Symbol:
We were required to add our initials in the middle of our NAND symbol.
Layout:
DRC:
Extracted layout:
LVS:
Part 2
XOR gate
Similar to the first part of this lab, we then needed to draft a schematic of a 2-input XOR gate using 6u/0.6u NMOS and PMOS MOSFETs and create a layout.
Schematic:
Symbol:
We were required to add our initials in the middle of our XOR symbol.
Layout:
DRC:
Extracted layout:
LVS:
Part 3
Full-Adder
We then begin creating the Full-Adder by simulating the logical operation of the gates for the 4 inputs possible, which are 00, 01, 10 and 11.
Gate schematic:
Gate output graph:
When you look at the graph of the outputs above, you notice that there are glitches due to the timing of the input pulses. There are glitches on both the rising and falling edges. Since the value is not consistent, when there is a change in the input, the gate reacts by causing a glitch in the pulse before stabilizing again.
Full-Adder schematic:
Full-Adder symbol:
Full-Adder layout:
DRC:
Full-Adder extracted layout:
LVS:
Full-Adder simulation schematic:
Full-Adder simulation output graph:
