Lab 5: EE 421L
Design, layout, and simulation of a CMOS inverter
Authored by: Kaylee Spencer
Email: spenck3@unlv.nevada.edu
Due: 10/09/2019
Lab Description: This lab is meant to teach us how to design, layout, and simulate a CMOS inverter with two different sets of parameters.
Prelab
Part 1
For the prelab, we needed to go through Tutorial 3. Below I have added images from the tutorial.
![](1.png)
![](2.png)
Next,
we created the layout for the inverter (shown below) and then created
an extracted layout. We then ran a DRC and LVS to ensure it worked
correctly.
![](3.png)
![](4.png)
![](5.png)
![](6.png)
![](7.png)
Finally, I created the schematic above and was able to run the simulation to give the DC response graph below.
![](8.png)
Lab
Part 1
12u/6u
First, we needed to start by creating a schematic and symbol for the inverter with a size of 12u/6u. We used a multiplierof M=1.
![](9.png)
![](10.png)
Similar to the prelab, we created a layout for the inverter as well as an extracted layout. After that, we ran a DRC and LVS.
![](11.png)
![](12.png)
![](13.png)
![](14.png)
48u/24u
We then followed the exact same steps as above, however we change the size to 48u/24u and set the multiplier to M=4.
![](15.png)
![](16.png)
![](17.png)
![](18.png)
![](19.png)
![](20.png)
Part 2
For
the next part of the lab, we needed to simulate the operation of both
the inverters we create for the following capactive loads: 100fF, 1pF,
10pF and 100pF. For each capacitive load, we were required to run it
with Spectre as well as UltraSim.
100fF
![](21.png)
![](22.png)
i
![](24.png)
1pF
![](25.png)
![](26.png)
![](27.png)
10pF
![](28.png)
![](29.png)
![](30.png)
100pF
![](31.png)
![](32.png)
![](33.png)
We then repeated the same steps above for the second inverter.
100fF
![](34.png)
![](35.png)
![](36.png)
![](37.png)
1pF
![](38.png)
![](39.png)
![](40.png)
10pF
![](41.png)
![](42.png)
![](43.png)
100pF
![](44.png)
![](45.png)
![](46.png)
lab5_ks.zip
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