Lab 5: EE 421L
Design, layout, and simulation of a CMOS inverter
Authored by: Kaylee Spencer
Email: spenck3@unlv.nevada.edu
Due: 10/09/2019
Lab Description: This lab is meant to teach us how to design, layout, and simulate a CMOS inverter with two different sets of parameters.
Prelab
Part 1
For the prelab, we needed to go through Tutorial 3. Below I have added images from the tutorial.
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Next,
we created the layout for the inverter (shown below) and then created
an extracted layout. We then ran a DRC and LVS to ensure it worked
correctly.
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Finally, I created the schematic above and was able to run the simulation to give the DC response graph below.
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Lab
Part 1
12u/6u
First, we needed to start by creating a schematic and symbol for the inverter with a size of 12u/6u. We used a multiplierof M=1.
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Similar to the prelab, we created a layout for the inverter as well as an extracted layout. After that, we ran a DRC and LVS.
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48u/24u
We then followed the exact same steps as above, however we change the size to 48u/24u and set the multiplier to M=4.
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Part 2
For
the next part of the lab, we needed to simulate the operation of both
the inverters we create for the following capactive loads: 100fF, 1pF,
10pF and 100pF. For each capacitive load, we were required to run it
with Spectre as well as UltraSim.
100fF
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i
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1pF
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10pF
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100pF
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We then repeated the same steps above for the second inverter.
100fF
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1pF
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10pF
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100pF
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