Design a circuit that takes a 9-11MHz clock signal and generates a 36-44 MHz clock signal.

Authored by: Kaylee Spencer

Email: spenck3@unlv.nevada.edu

Part 1 Due: 11/13/2019

Part 2 Due: 11/20/2019

Lab Description: This lab was meant to design a 4x multiplier, which essentially would take the input clock, multiply it by 4 and produce an output. The clock also needed to have a 50% duty cycle.

Lab

Part 1

In this part of the lab, we create a clock multiplier, which will have a schematic similar to the one below, consisting of XOR’s and buffers.

I first started off by creating an XOR gate, which we had previously done in Lab 6. An XOR gate looks at both the input signal as well as the delay and creates an output from the two. An XOR gate is also known as an “edge detector.” The function of an XOR is AxorB = AB’ + A’B, which states that when one input is high, the output is high. However, if both or neither inputs are high, then the output is low.

(XOR schematic)

(XOR symbol)

I then created my first buffer, which would be used to delay my input signal when placed in my simulation schematic. My buffer consists of 6 inverters. The 3 inverters on the left are what cause the delay from my output and the 3 inverters on the right are what cause a fast edge for the delay signal.

(buffer 1 schematic)

For my delay buffer, I used 3 PMOS’ with width 12u and length 7.5u and 3 NMOS’ with width 6u and length 7.5u. To get a 50% duty cycle, the delayed signal needs to rise directly in the middle of the input signal. I was able to get this with a width of 7.5u. As for my fast buffer, I used PMOS’ and NMOS” with width 12u and length 0.6u, which was able to give me a sharper edge. Using a smaller length allows for a sharper edge while using a larger length makes the edge slower and fade out.

(buffer 1 symbol)

(frequency multiplier 2x, stage one schematic)

Next I added my buffer 1 to the schematic above to test my first stage of the clock multiplier. For the input signal, I used a 111ns time period (9MHz). The difference between my input signal and delayed signal is 27.2ns and the difference between my delayed signal and my output signal is 28.7ns. As you can see below, for my 2x clock multiplier, I was able to achieve almost a perfect 50% duty cycle, however the edges of the output signal aren’t very sharp. To create a sharper edge, we are able to add a small buffer directly after the XOR gate.

(frequency multiplier x2, stage one graph)

Below is the schematic of my sharp buffer, which will help smooth out the signal as well as create a sharper edge. Since the edges are only slightly off, only two inverters (20/1 PMOS’ and 10/1 NMOS) are needed.

(sharp buffer schematic)

(sharp buffer symbol)

(frequency multiplier 2x with sharp buffer, stage one schematic)

When the sharp buffer was added, the output signal edges were able to clean up and create a more pleasing output signal.

(frequency multiplier 2x with sharp buffer, stage one graph)

Similar to buffer 1, I created buffer 2 for my second stage of my clock multiplier. For my delay buffer, I used 3 PMOS’ with width 12u and length 5.55u and 3 NMOS’ with width 6u and length 5.55u. As for my fast buffer, I used the same width and length as the fast buffer from my first buffer. I used a 111ns time period (9MHz), which gave me a pulse width of 55.5ns.

(buffer 2 schematic)

(buffer 2 symbol)

I was able to get a delay of 15.7ns, about ¼ between my buffer 2 output signal and my overall output signal, which would give me a 4x clock multiplier output in the next step. To ensure I have sharp edges, I added a buffer after the XOR gate for the second stage as well.

(frequency multiplier 2x with sharp buffer, stage two schematic)

(frequency multiplier 2x with sharp buffer, stage two graph)

Finally, I was ready to create my 4x clock multiplier. I simply combined the first stage and second stage I had previously built to create the schematic below. I decided to stay with using a 111ns time period (9MHz) as I did in the single stage simulation schematics.

(frequency multiplier x4 with sharp buffers schematic)

Below, I was able to show the signals for my input, buffer 1 output, XOR 1 output (2x clock multiplier), buffer 2 output and the overall output (4x clock multiplier). My pulse width of my buffer 2 output is 31.3ns. For my 4x clock multiplier output signal, I was able to get a difference of almost exactly 50% duty cycle (14.5ns).

(frequency multiplier 4x with sharp buffers graph)

I then tested a few different frequencies and voltages.

(111ns period, 9 MHz frequency, VDD = 7V)

(105ns period, 9.5 MHz frequency, VDD = 6V)

(100ns period, 10 MHz frequency, VDD = 5V)

(95 ns period, 10.5 MHz frequency, VDD = 4V)

(90 ns period, 11 MHz frequency, VDD = 3V)

Part 2

In this part of the lab, we were required to create layouts for each component of the clock multiplier and then create a layout with all of them combined.