EE 421L Digital Electronics Lab
Ja Manipon
maniponj@unlv.nevada.edu
Fall 2016

  


Description
Lab 1Laboratory introduction, generating/posting html lab reports, installing and using Cadence
Lab 2Design of a 10-bit digital-to-analog converter (DAC)
Lab 3Layout of a 10-bit DAC
Lab 4IV characteristics and layout of NMOS and PMOS devices in ON's C5 process
Lab 5Design, layout, and simulation of a CMOS inverter
Lab 6Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder
Lab 7Using buses and arrays in the design of word inverters, muxes, and high-speed adders
Lab 8Generating a test chip layout for submission to MOSIS for fabrication

Project
 

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