Lab 3 - EE 421L 

Authored by Ja Manipon
maniponj@unlv.nevada.edu
9/20/16
Lab 3 Design Files

Pre-Lab

• Back-up all of your previous work from the lab and the course.
  
• Finish Tutorial 1.
  

This lab will focus on the layout of the 10-bit DAC you designed and simulated in Lab 2

• Use the n-well to layout a 10k resistor as discussed in Tutorial 1
  
• Discuss, in your lab report, how to select the width and length of the resistor by referencing the process information from MOSIS
• Use this n-well resistor in the layout of your DAC
• Discuss, in your lab report, how the width and length of the resistor are measured
  
• Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked)
• All input and output Pins should be on metal 1
• DRC and LVS, with the extracted layout, your design (show the results in your lab report)
• Zip up your final design directory and place it in the lab3 directory, with a link on your lab report, so the grader can examine both the layout and schematic (and simulations)

N-Well Layout of 10K resistor

Layout and Extracted

Description

This is my design of a 10K N-Well Resistor. In order to calculate the dimensions of this N-Well, I used the formula R = R(per Square)*(L/W). The minimum width for this design is 3.6um but I bumped it up to 4.5um and added two contacts onto the Ntaps. I plugged the 4.5um into the formula as well as the 800 Ohms per square and rearranged some of the variables to calculate the Length (L = (R*W)/R(Per Square)) L = (10K*4.5u)/800 L = 56.25um This is how I calculated the length of the N-Well. In the tutorial, it asks you to put in a length of 56um however 56um does not land in the .15um grid per the DRC. So I had to add the .1um in order to make it land on the grid. 56.25um would also work since 56.25/.15 = 375.

DAC Layout with 10K N-Well Resistor

Layout and Extracted	DAC Inputs and Outputs	Description
		I based the layout on the previous schematic that was created from the previous lab. The resistor that is being used is the one I created going through Tutorial 1. The schematic had 31 resistors in total, four resistors for B0 and three resistors for the rest of the inputs.  First I started with B0 adding the four resistors according to the schematic, then I copied the first three resistors with an array of 9 to take care of the rest of the inputs. After that, I created the metal1 wire to connect the resistors in parallel like in the schematic and copied the wire 9 times to connect the rest of the resistors.Once I completed copying and pasting the metals and resistors, I DRC'd and Extracted the layout for LVS.

DRC and LVS of DAC Layout

DRC and LVS	Schematic Used for the LVS
Description After I ran the DRC on the layout with no errors, I extracted the layout and ran the LVS with the schematic that was created in the previous lab. Net-lists matched and the image above is output from the LVS

Extracted Simulation vs. Schematic Simulation

Schematic	Extracted	Simulation
		Simulation of Ideal ADC to My DAC
		Simulation of my 10Bit DAC with everything grounded except for B9 with a 10pF load
		Simulation adding a 10K resistor as the load
		Simulation adding a 10pF capacitor as the load
		Simulation adding a 10K Resistor || 10pF Capacitor as the loads.

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