Project - EE 421L 

Authored by Ja Manipon
maniponj@unlv.nevada.edu
11/16/16

Lab Files

• First half of the project (just the detector schematics, no layout), of your design and an html report detailing operation (including simulations), is due at the beginning of lab on Nov. 16.
• Your detector circuit should show various inputs to verify it works
• Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu. 

First Half (Schematic)

D Flip Flop

Schematic		Created the schematic, based from the book as well as given in the lab. Has 4 T-Gates and 4 Transistors. This is an edge triggered D Flip Flop and needed for the Detector
Symbol		Next I created a symbol for it.
Simulation Schematic		After the symbol was made, I used it for the simulation.
Simulation		Based on the simulation, it appears to be functioning correctly. The output is what it is on the input only on the  rising edge

6 Input NAND Gate

Schematic		Next I created a 6 Input NAND gate to detect the input 101011
Symbol		I created a symbol for it to be used in the Detector schematic

Detector

Schematic		I added the six D flip flops to hold the serial value and all the outputs go to the NAND gate. I inverted it for the output to go high when the sequence is detected.
Simulation		From the simulation, detector works correctly when inputted the serial data and it goes high once the entire string goes in and only stays high for one clock cycle.

Second Half (Layout)

	D Flip Flop	6 Input NAND	Inverter
Layout
Extracted
DRC
LVS
Comments	The D Flip Flop is organized with all my Inverters on the left side and my Transmission Gates are on the right side. The inverters are organized left to right based on the schematic. The Transmission Gates were able to be combined due to the source or drains were connected based also on the schematic	With the NAND gate, I based it on the previous 2 Input NAND gate from previous labs. I increased the multiplier to 6 on both the NMOS and PMOS due to an increase of inputs.	This inverter was created from my previous labs and was needed for the output of the NAND gate in order to have it output high when the sequence was detected

Detector

Layout
Extracted
DRC
LVS
Comments	With this design I lined everything in a row in order to have the VDD and GND rails go straight across layout. Then I connected every instance with a metal3 wire.

D Flip Flop Extracted Simulation

Simulation
Netlist
Comments	Ran an extracted simulation to make sure the D Flip Flop to make sure the functionality of it is still the same.

Detector Extracted Simulation

Simulations 101011 111111 000000 111000 000111
Netlist
Comments	I ran a few extracted simulations with different serial inputs to make sure my layout works correctly. When the serial input does not match output voltage never goes high and simulation zooms in to the mV range.

Detector on Padframe

Schematic
Layout
LVS/DRC
Comments	I layed a padframe for the Detector and connected it to corresponding pins on the schematic. Added a small buffer to the output as stated in the lab.

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