Lab 2 - EE 421L

Authored by Ja Manipon

maniponj@unlv.nevada.edu

9/14/2016

Pre-lab work

Back-up all of your work from the lab and the course.
Read through this entire lab write-up before doing the pre-lab
Download lab2.zip to your desktop.

This archive contains a simulation example using an ideal 10-bit Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC).

Upload this zip file to the design directory on the server that you are running Cadence from, e.g., Tutorial_1, CMOSedu, etc.

Note that it's assumed you are using the NCSU Cadence Design Kits.

Unzip this directory and add, to your cds.lib in the design directory, the following statement (assuming the design directory is CMOSedu):

DEFINE lab2 $HOME/CMOSedu/lab2

Start Cadence from the design directory.

Use the Library Manager and navigate to the lab2 Library as seen below.

Open the schematic view of the cell sim_Ideal_ADC_DAC.

This cell contains the ideal 10-bit ADC and DAC

Run the simulation (Launch the ADE, Session -> Load State -> Cellview -> OK, press the green start button) to get the following.

Make sure you understand how to change the background color, line thickness, and type of line (e.g. solid, dashed, etc.)

Prior to coming to lab make sure you understand how the input voltage, Vin, is related to B[9:0] and Vout (the quiz may ask a question about this).
In your lab report: 1) provide narrative of the steps seen above, 2) provide, and discuss, simulation results different from the above to illustrate your understanding of the ADC and DAC, 3) explain how you determine the least significant bit (LSB, the minumum voltage change on the ADC's input to see a change in the digital code B[9:0]) of the converter. Use simulations to support your understanding.
Backup your webpages and design diretory.

I backed up all images and files on my local and Google Drive

Local	Cloud

Ideal ADC to DAC Backing up Files

Once I added my zip files and defined my library for lab 2, I went into the library and opened up the schematic as well as run the simulation and these are the resulting images below

Schematic	Simulation	Description
		The purpose of the ADC is to convert Analog Signal into a Digital Signal and the DAC is to convert Digital Signal into Analog Signal. The purpose of the DAC is to imitate the analog signal since computers cannot grasp the infinite amount of points an analog signal can give. When the signal goes through the DAC, the output looks like a staircase as shown to the side. The amount of steps is determined by how many bits the DAC contains. The more bits and the more precise it is and the more it looks like the original Analog Signal.

Calculating LSB

1 LSB = VDD/2^n

In order to calculate the voltage for the Least Significant Bit is the Supply Voltage divided by 2 to the power of n-bits. For this 10-Bit DAC and assuming we are using a 5V power supply, the voltage for the LSB is 5V/2^10 = 4.88mV. This is our resolution for the 10-Bit DAC.

Post-Lab:

Design of a 10-Bit Digital-to-Analog Converter (DAC) Schematic

Determining the Output Resistance of the DAC

Visual of DAC Output Resistance

Explanation

With how the DAC is arranged with a bunch of resistors in series and parallel you can calculate the output resitance to be R. The image to the left shows a basic DAC with 3 Bits. As shown in the image when calculating the output Resistance, which should be R, shows that the LSB has 2R || 2R. This would result it being R. The next step shows R is in series with R making it 2R thus repeating the process of 2R || 2R. Once it reaches the MSB, the result would be R. This can be applied to a DAC with n-amount of bits.

((((2R || 2R) + R) || 2R) + R) || 2R) = R

Schematic and Symbol of DAC

Schematic

Symbol

Description

I created the schematic for the DAC based on the schematic of resistors that was given in the prelab and that is shown to the left. Once I finished building the schematic I went into Create->Cellview and created a symbol. I delated all the uneccesary lines for the symbol thus creating the symbol to the left as well..

Grounding the DAC symbol except for B9 and adding 10pF capacitor load

Schematic	Simulation	Description
		Adding the capacitor creates a delay of roughly 70ns. This can be estimated by Td = 0.7RC --> 0.7(10K)(10p) = 70ns

Replacing Ideal DAC with own DAC

New Schematic	Simulation	Description
		Once I replaced the Ideal DAC with my own design, the simulation comes out very similar to the original schematic. The steps are not as refined as the ideal but still

Adding Different Loads

Schematic	Simulation	Description
10K Resistor		When adding a 10K resistor as the load, the sine wave follows the same trend however the voltage is about half the input voltage. Adding this 10K resistor turns the DAC into a voltage divider since we determined the output resistance is 10K and Vout = Vin(10K/(10K+10K)) will give 1/2Vin.
10pF Capacitor		When adding a 10pF capacitor, there is a loss of amplitude as well as a delay of 75ns
10K Resistor \|\| 10pF Capacitor		Adding a 10pF capacitor and 10K resistor results in the output voltage to have a loss of altitude as well as causing a delay by 50ns.

What happens if the resistance of the switches isn't small compared to R?

This would cause the input to encounter high impedance and causing the voltage that is being inputted not go through the DAC, thus causing some errors in the simulation.

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