Lab 4 - EE 421L 

Authored by Ja Manipon
maniponj@unlv.nevada.edu
9/28/16

Pre-Lab

• Back-up all of your work from the lab and the course. 
  
• Read through this lab before starting it.
  
• Go through Tutorial 2 seen here.
  
• In the simulations in this lab the body of all NMOS devices (the substrate) should be at ground (gnd!) and the body of all PMOS devices (the n-well) should be at a vdd! of 5V. 
  

• Generate 4 schematics and simulations (see the examples in the Ch6_IC61 library, but note that for the PMOS body should be at vdd! instead of gnd!):
  
• A schematic for simulating ID v. VDS of an NMOS device for VGS varying from 0 to 5 V in 1 V steps while VDS varies from 0 to 5 V in 1 mV steps. Use a 6u/600n width-to-length ratio.
  
• A schematic for simulating ID v. VGS of an NMOS device for VDS = 100 mV where VGS varies from 0 to 2 V in 1 mV steps. Again use a 6u/600n width-to-length ratio.
  
• A schematic for simulating ID v. VSD (note VSD not VDS) of a PMOS device for VSG (not VGS) varying from 0 to 5 V in 1 V steps while VSD varies from 0 to 5 V in 1 mV steps. Use a 12u/600n width-to-length ratio.
  
• A schematic for simulating ID v. VSG of a PMOS device for VSD = 100 mV where VSG varies from 0 to 2 V in 1 mV steps. Again, use a 12u/600n width-to-length ratio.  

• Lay out a 6u/0.6u NMOS device and connect all 4 MOSFET terminals to probe pads (which can be considerably smaller than bond pads [see MOSIS design rules] and directly adjacent to the MOSFET (so the layout is relative small).
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout.
  

• Lay out a 12u/0.6u PMOS device and connect all 4 MOSFET terminals to probe pads.
• Show your layout passes DRCs. 
• Make a corresponding schematic so you can LVS your layout.
  

Schematics and Simulations for NMOS/PMOS

Schematic	Simulation	Description
		ID v. VDS Here I simulate the ID v. VDS for the NMOS. I ran a parametric analysis resulting in 5 different curves. I varied the VGS from 0 to 5 V in 1V steps while the VDS varied from 0 to 5V in 1mV steps.
		ID v. VGS Here I simulate the previous circuit but ran a normal simulation and got this curve. VDS = 100 mV and I varied the VGS from 0 to 2V in 1mV steps.
		ID v. VSD Next, I simulate the ID v. VSD for the PMOS circuit. I ran a paraemetric analysis resulting to a similar 5 different curves. I varied the VSG from 0 to 5 V in 1V steps while VSD varied from 0 to 5V in 1 mV steps.
		ID v. VSG Similary, I ran another simulation on the previous with a change to the VSD to 100mV and varied the VSG from 0 to 2V in 1mV steps and got this curve

Design of Pad

	Images	Description
Schematic		This is the schematic of the pad with just an inputoutput pin labeld pad
Symbol		I created a symbol from the schematic and resulted in a box with a terminal
Layout		I designed the layout with 3 different layers. The pad being the largest for a template, then the metal3 in the center of that and a glass layer smaller as well as center of the metal3.

Layout of NMOS 6u/0.6u 

	Images	Description
NMOS_IV Schematic		This is the schematic I made for the NMOS_IV
Symbol		This is the symbol I created from the NMOS_IV Schematic
NMOS Pad Schematic		Here is the schematic design of the NMOS using the symbol created in the tutorial. Each terminal is connected to a respective pad
Layout		This is the layou design of the NMOS connected to the pads through metal3 wires
Layout Zoomed		Here is a zoomed image of the NMOS in the center of the pads
DRC & LVS		Once I had the extracted and schematic views completed, I ran the DRC for the layout and ran an LVS for the extracted and schematic

Layout of PMOS 12u/0.6u

	Images	Description
PMOS_IV Schematic		This is the schematic for the PMOS_IV
Symbol		This is the symbol I created from the PMOS_IV schematic
PMOS Pad Schematic		The schematic for the PMOS is similar to the NMOS. All that needed to be swapped was the NMOS and the schematic was complete
Layout		Similarly with the layout I had to swap out the NMOS with a PMOS layout and reconnected the wires
Layout Zoomed		This is a zoomed in image of the layout with the PMOS in the center
DRC & LVS		Once I had both the layout and schematics completed, I ran a DRC for the layout and ran an LVS for the extracted and schematic views.

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