Lab 7 - EE 421L 

Authored by Ja Manipon
maniponj@unlv.nevada.edu
11/16/16
Lab Files

Pre-Lab

• Back-up all of your work from the lab and the course.
  
• Go through Cadence Tutorial 5.
  
• Read through the lab in its entirety before starting to work on it
  

• Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
  
• Provide a few simulation examples using these gates.
  
• Create a schematic of a 2-to-1 DEMUX/MUX (and the symbol).
  
• Simulate the operation of this circuit using Spectre and explain how it works.
  
• Make sure to show, using simulations, how the circuit can be used for both multiplexing and de-multiplexing
• Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
  
• Include an inverter in your design so the cell only needs one select input, S (the complement, Si, is generated using an inverter).
  
• Use simulations to verify the operation of your design.
  
• Finally, draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).
  
• Create an adder symbol for this circuit (see the symbol used in lab6).
  
• Use this symbol to draft an 8-bit adder schematic and symbol.
  
• Simulate the operation of your 8-bit adder
  
• Lay out this 8-bit adder cell (*note* that this is the only layout required in this lab).
  
• Show that your layout DRCs and LVSs correctly.

Creating 4 Bit Inverter

Schematic		For the 4-Bit Inverter, I instantiated an array of 4 Inverters and connected bus wires for the pins
Symbol		Next, I created the symbol for the 4-Bit Inverter
Simulation Schematic		After, I created Schematic for a simulation of the 4-Bit Inverter attached to each bit is a different size capacitor.
Simulation		From the simulation, the capacitor are affecting the output of the inverters. Based on the simulations, the rise and fall time are increased when the capacitors are increased as well.

Creating 8 Bit Logic Gates

NAND Gate

• Similar to the Inverter, I ran the same process for schematic and symbol.

Schematic
Symbol
8 Bit Schematic
8 Bit Symbol

NOR Gate

• Again I did the same process for the NAND gate for the NOR gate.

Schematic
Symbol
8 Bit Schematic
8 Bit Symbol

AND Gate

• With the AND gate, I repeated the same process for the NAND except in the schematic of the NAND I added an Inverter on the output

Schematic
Symbol
8 Bit Schematic
8 Bit Symbol

OR Gate

• The OR gate had the same process as the NOR, except in the schematic I added an Inverter on the input

Schematic
Symbol
8 Bit Schematic
8 Bit Symbol

Inverter Gate

• With the 8-Bit inverter, I used the 4-Bit made earlier and extrended the it to 0:7 instead of 0:3

Schematic
Symbol
8 Bit Schematic
8 Bit Symbol

Gate Simulations

• Once all the gates were built, I simulated all the same time and in a similar fashion as the 4-Bit inverter each with a different capacitor size
• As from the simulation, we see the similar effect from the 4-Bit Inverter simulation, the higher the capacitor, the rise and fall time increases

Schematic
Simulation

Creating and Simulating 2 to 1 MUX/DEMUX

• I created the MUX/DEMUX based on the schematic given by the lab
• In order for it to be both a MUX and DEMUX, I changed the A, B and Z pins to input/output
• After I created the symbol, I placed it into the schematic for the simulation
• The simulations ran below, shows the MUX/DEMUX is running perfectly
• With the DEMUX simulation, the results are slighltly weird due to the fact when the input goes to the other gate, the previous gate will stay on the output just before switch

Schematic
Symbol
Simulation Schematic (MUX)
Simulation (MUX)
Simulation Schematic (DEMUX)
Simulation (DEMUX)

Creating 8-bit 2 to 1 MUX/DEMUX

• With the 8-Bit 2 to 1 MUX/DEMUX, the process is the same as the previous 8-Bit gates and the simulation ran was similar to other ones as well

Schematic
Symbol
Simulation Schematic (MUX)
Simulation (MUX)
Simulation Schematic (DEMUX)
Simulation (DEMUX)

Creating and Simulating AOI Full Adder

• Instead of using logic gates from before to create our Full Adder, we used on in the textbook called the AOI Full Adder
• This full adder is much simpler in that all the PMOS and NMOS have compliments of each other, thus laying out the transistors easy to connect
• Once I layed out and extracted the Full Adder, I ran the LVS and then ran both the schematic and extracted simulation verifying it is functioning correctly

Schematic
Symbol
Layout
Extracted
DRC/LVS
Simulation Schematic
Simulation
Extracted Simulation

Creating 8-Bit AOI Full Adder

• With creating the 8-Bit AOI Full Adder, I did the same process as the other 8-Bit gates. In addition to that process I had to layout the 8-Bit Adder.
• Once I finished laying out and extracting the circuit, I ran the LVS and they netlists matched .
• After they matched, I ran both the schematic and extracted simulation and it functioned prefectly

Schematic
Symbol
Layout
Extracted
DRC/LVS
Simulation Schematic
Simulation
Extracted Simulation

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