EE421L - Digital Integrated Circuit Design, Fall 2020
Lab 4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process
Lab 5 – Design, layout, and simulation of a CMOS inverter
Lab 6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder
Lab 7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders
Lab 8 - Generating a test chip layout for submission to MOSIS for fabrication
Final Project - High Speed Digital Receiver
During the pandemic I have decided to try baking to relax and gain some skills. Below are a couple of my latest creations. I have a pizza addiction, so most of my projects will be pizza and pizza-accessories.
Chicago-style Deep Dish Pizza:
Kachapuri (Georgian cheese stuffed bread with egg on top):
Stromboli:
Home-made cheese crackers (much better than cheese-nips):
My partner in crime:
