Lab 6 - EE 421L Digital Integrated Circuit Design, Fall 2020

Author: William Wherry

10/21/2020

Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full-Adder

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 4 seen here.
• Read through the lab in its entirety before starting to work on it

Following Tutorial4, the schematic and symbol for the 2-input NAND gate come out like this:

Next, we make a circuit to test it:

Settings and results:

Now we have to layout the design.

DRC & LVS results:

The result says our design is good, but if you look at the schematic it says the MOSFETs are all 6u/0.6u. The layout's PMOS is 12u/0.6u. This should throw back an error, but the LVS is not checking our layout sizes against our schematic sizes unless we enable the option. 

Now if we run the LVS again we will get an error.

We will have to be mindful of checking the size of our layouts against the size of the schematic parameters in order to design our circuits correctly. 

Backing up our work:

As always we must backup our work. I backed up the prelab by zipping it up and uploading it to my google drive along with all of my other lab work.

With our NAND gate design tested and backed up, prelab 6 is concluded.

• Draft the schematics of a 2-input NAND gate (Fig. 12.1), and a 2-input XOR gate (Fig. 12.18) using 6u/0.6u MOSFETs (both NMOS and PMOS)
• Create layout and symbol views for these gates showing that the cells DRC and LVS without errors
• ensure that your symbol views are the commonly used symbols (not boxes!) for these gates with your initials in the middle of the symbol  
• ensure all layouts in this lab use standard cell frames that snap together end-to-end for routing vdd! and gnd!
• use a standard cell height taller than you need for these gates so that it can be used for more complicated layouts in the future
• ensure gate inputs, outputs, vdd!, and gnd! are all routed on metal1
• Use cell names that include your initials and the current year/semester, e.g. NAND_jb_f19 (if it were fall 2019)
• Using Spectre simulate the logical operation of the gates for all 4 possible inputs (00, 01, 10, and 11)  
• comment on how timing of the input pulses can cause glitches in the output of a gate

• Using these gates, draft the schematic of the full adder seen below 
• Create a symbol for this full-adder (example)
• Simulate, using Spectre, the operation of the full-adder using this symbol  
• Layout the full-adder by placing the 5 gates end-to-end so that vdd! and gnd! are routed
• full-adder inputs and outputs can be on metal2 but not metal3
• DRC and LVS your full adder design 

2-input NAND gate:

First we have to make a 2-input NAND gate. We made one in the prelab, but noticed that the layout size of the PMOS was not the same as the schematic size, so we have to fix that to not get a size mismatch error.

Schematic and Symbol:

Now for the layout we have to make sure both the PMOS and NMOS are 6u/0.6u. We should also take into consideration that the layouts we make will be used later in the lab for more complex designs that need to be easily routed to vdd and gnd, so we will add a bit of space between the PMOS and NMOS for routing later. I decided that 15.3u was probably enough space and used that as my standard spacing for the lab.

Then we DRC and LVS the schematic and extracted layout. As you can see I had no errors, unlike in the prelab.

2-input XOR gate:

Now that the 2-input NAND is complete, it is time to work on the 2-input XOR gate. The XOR gate requires 6u/0.6u MOSFETS and consists of two inverters to invert the inputs for use with a set of PMOS and NMOS. The schematic and symbol I designed are shown below.

Schematic and symbol:

For the layout of this schematic, I decided to use an inverter design from an earlier lab to make things a little easier. I modified it a bit to make sure it was the correct size MOSFETs as well as the same 15.3u distance gap between the top and bottom so it could easily fit in my designs for this lab. I then made a copy of that inverter and named the first one InverterA and the second InverterB, modifying their input and output to match the schematic's inverters A, Ai, B, Bi ports. This step may not have been necessary, but I found it to be good practice and I think it saved some time in the end. Below are my inverters.

Inverters used in XOR design:

   
Using the method of instancing and flattening instances shown in the tutorial 4, I tried to make life easier by dropping in instances of each of my inverters as well as two instances of my NAND I made earlier, since it had the basic parts I needed to layout the XOR gate (4 PMOS and 4 NMOS total in addition to the two inverters).
   
Instantiating the inverters and NANDs (before flattening):

   
I quickly realized that this setup was not ideal (after trying in vain to make efficient connections), so I had to move around the parts shown above, keeping in mind what would need to be connected. I drew a few pictures to help me plan this part, rather than just wing it. I wasted a lot of time because my metal 1 and metal 2 layers kept ending up being too close to each other, so planning is key in this phase of design. After a few hours of pain, my final layout design came out as show below.
   

   
I tried my best to keep inputs and outputs within the overall block of the layout, because I knew later on I would need to instanciate this layout to make a Full Adder. If there were parts sticking out it would be very hard to place the design adjacent to another layout instance. That's why my A, B, and AxorB outputs are tucked away inside the center and not poking out. Also note that a requirement for the design was that inputs and outputs must be on metal 1.
   
DRC & LVS results:


   
Testing the gates:
 Next the gates have to be tested. I made a simulation circuit that would test my inverter, 2-input NAND, and 2-input XOR gates all at the same time in one circuit. 
   

   
The A and B pulse sources will go to all the gates and using the ADE we can just check each graph as needed. The settings for the pulses are shown below as well as the ADE settings.
   


Since the two most complex gates' truth tables only have four entries each, I only needed four changes of pulse to hit each possibility. One pulse changes between 1 and 0 every 100ns, and the other changes between 1 and 0 every 200ns. The total simulation is for 400ns, so that will cover all possibilities.
   
Sim Results:   
   
Inverter:

   
2-input NAND:

   
2-input XOR:

   
   
Notes about possible glitches:
Glitches can be caused if the rise/fall times of the pulses take too long. As shown below, if you increase the rise and fall time by a bit you start to get false readings at the outputs of your gates. This can obviously affect expected operation of your circuit and should be kept in mind. I only increased the rise and fall times from 1ns to 15ns and nearly got an unexpected 1 and 0 in the output graph. At the very least, this could cause periods of time where the output is neither 1 nor 0, or at worst it could cause unexpected 1 or 0 output.

   

   
   
Designing a Full Adder:
   
Next, we have to design and simulate a full adder using the gates that we created earlier in the lab. A full adder can be made up of NAND and XOR gates, with the inputs a, b, cin and the outputs cout and s (for sum). Below is my schematic and symbol I made for the full adder.
   
Schematic and symbol:


   
Next, we have to layout the full adder, which for me was a lot easier than laying out the XOR gate. This is because I planned ahead for this layout to be painful if I was not organized in my designs early on. As mentioned earlier, I tried to tuck inputs and outputs inside the designs in order to easily place instances of the gates next to each other. The only issue I had was that my ntap and ptaps were not laid out as nicely when placed next to each other as I would have wanted. I overlooked these because I was so focused on input/output connections being clean and organized. Below is the layout that I came up with. Note that for this layout, outputs can be on metal2, but not metal3. the layout required 2 XOR gates and 3 NAND gates, so I just instanced them in, put them next to eachother and began connecting the inputs and outputs as the schematic had shown.
   
Layout and extracted layout:


   
DRC & LVS results:


   
As you can see, the full adder has passed the DRC and LVS and can now be tested.
   
Simulating the full adder:
   
To simulate the full adder, I made a similar circuit to the first gate testing circuit, except this time I used 3 pulse sources, since the circuit has 3 inputs. When testing a logic gate, your pulses should each be twice the width of the last pulse width, similarly to how the truth tables are set up. My simulation circuit used the exact same pulses as the first sim circuit, except the third pulse source had a width twice as long as the second pulse. This way, I could hit all possible inputs and outputs in 8 steps.
   
Simulation circuit:

   
Simulation results:

   
Truth table for full adder:

You can see that my results match up perfectly with the truth table for a full adder, so it appears that my design was a success!
   
Backing up our work:
As always we must back up our work. I prefer to back up my work by downloading the working directory, zipping it up, and uploading it to my google drive.
   

   
   
With our gates and full adder laid out, tested and backed up, lab 6 is concluded.
   
   

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