Lab 3 - EE 421L Digital Integrated Circuit Design, Fall 2020

Author: William Wherry

9/13/2020

Lab description:

This lab will focus on the layout of the 10-bit DAC you designed and simulated in Lab 2

Prelab Work:

• Back-up all of your previous work from the lab and the course.
• Finish Tutorial 1 seen here. 

As always, we backup our previous work just in case. 

Tutorial 1 involves designing a schematic for a simple voltage divider using two 10k-resistors. We have to not only create the schematic for that voltage divider, but also create a symbol and layout for it, so it could theoretically be manufactured. First, we create a schematic for the voltage divider.

Then we create a symbol for it.

Then we have to make a layout for it, which is the technical file that could be used to manufacture the component. We made a 10k resistor layout earlier in the tutorial that we will simply use as an instance twice. We calculated that the resistor would need to be of 4.5u width and 56.1u long in order to achieve about 10k ohms resistance with a sheet resistance of ~800 ohms per square. If we divide 56.1 by 4.5 we can see that 56.1/4.5 = 12.47squares * 800 = ~9,975 ohms. Keep in mind that the DRC file checks if the dimensions are divisible by 0.15 because that is what is required by the process we are using. 56.1/.15 = 374 and 4.5/.15 = 30, so our DRC should give us no problems. Laying out our resistor looks like this:

We check the DRC for errors, then verify-> extract, then check our extracted resistor for the value of resistance Cadence has calculated.

As you can see, our resistor came out pretty close to 10k ohms at 10.21k ohms. We can now use this resistor we created as an instance in our voltage divider for tutorial 1 as seen below.

We connect the resistor pins with Metal 1 and create pins with the same names as our voltage divider symbol and schematic. We can then check the DRC again, extract this layout, then check the LVS against the schematic to see if they match up. With our 10k resistor and voltage divider successfully created and backed up, prelab 3 is concluded.

• Use the n-well to layout a 10k resistor as discussed in Tutorial 1 
• Discuss, in your lab report, how to select the width and length of the resistor by referencing the process information from MOSIS
• Use this n-well resistor in the layout of your DAC
• Discuss, in your lab report, how the width and length of the resistor are measured 
• Ensure that each resistor in the DAC is laid out in parallel having the same x-position but varying y-positions (the resistors are stacked)
• All input and output Pins should be on metal 1
• DRC and LVS, with the extracted layout, your design (show the results in your lab report)
• Zip up your final design directory and place it in the lab3 directory, with a link on your lab report, so the grader can examine both the layout and schematic (and simulations)

For this lab we are going to design the layout of our 10-bit DAC from lab 2. We're going to do this efficiently by using instances of our 10k resistor we designed from Tutorial 1. In general, to design layouts in Cadence you must know the design rules, which are provided by the company that designed the process you are using. When we check the DRC against our design, we are checking if our design matches these manufacturing rules. We know from our design rules that the minimum width of our resistors is 12 lambda, where lambda is 300nm, which means a minimum width of 3.6um. From that minimum, our design dimensions have to be a multiple of 0.15um. That's why we chose 4.5um as the width and 56.1um as the length of our resistor in order to achieve a 10k ohm resistance using a sheet resistance of about 800 ohms per square, as per Tutorial 1 (shown in the prelab). An easy way to check that your length and width is correct is by pressing K and using the ruler to check your dimensions, but another way is to select the nwell rectangle that you plan to be your resistor, press Q, and manually set the dimensions in the properties box. 

To begin with, we have our schematic and symbol of our 10-bit DAC from lab 2.

Now we will design a layout using the 10k resistor layout from Tutorial 1. We could just place a whole bunch of instances of the 10k resistor, but a more efficient way is to create a layout for the 2R_R symbol used in the DAC schematic. That way we can place ten 2R_R instances rather than try to evenly space out 30 10k resistors. We create the layout, then DRC check it, then extract the layout, then LVS it to make sure it matches up. Once that is done we can instantiate it in our DAC schematic.

Now we create a layout for the 10-bit DAC and begin placing instances of our 2R_R layout. We can connect the "Top" and "Bottom" pins using Metal 1, which is a requirement of lab 3. We can then add the corresponding pins that we require (making sure their names match the 10-bit DAC schematic and symbol pin names) by selecting metal 1 and creating input or output pins as needed. 

You can see in the area surrounded by the yellow square that our layout we created for 2R_R has allowed us to efficiently place our resistors in a uniform fashion. This not only saves time in the long run, but allows for more symmetrical designs and less sloppy work. Now we continue placing instances of 2R_R until our layout is complete. 

As always we must back up our work. I back up my work by downloading the lab design directory as well as the webpage files, zip them up and email them to myself.

With our 10-bit DAC layout completed and our work backed up, lab 3 is concluded.

Return to William Wherry Labs Directory