Lab 7 - EE 421L Digital Integrated Circuit Design, Fall 2020
Author: William Wherry
Email: wherrw1@unlv.nevada.edu11/4/2020
Using buses and arrays in the design of word inverters, muxes, and high-speed adders
Prelab content:
- Back-up all of your work from the lab and the course.
- Go through Tutorial 5 seen here.
- Read through the entire lab before starting it.
Backing up our work:
As always, we must back up our work. I back up my work by downloading the directory and uploading it to my Google Drive.
Following
Tutorial 5, we are going to design a ring oscillator. The ring
oscillator will be 31 stages using the inverter we made in Tutorial 3.
First,
we will make it the inefficient way, then we will use a concise method.
We simply string together 31 of our inverter symbols in a row, with a
wire looping back to the very start. We also need a VDD off to the side
set at 5V for the inverters to work. This can be done with the global
settings, or with a dc source attached to the vdd symbol, like I have
done. I named the output wire "osc_out".
Simulation Results:
After
setting the initial voltage of "osc_out" to 0V as shown above, the
simulation results show the oscillator doing its job - oscillating.
This type of circuit can be used to test the speed of the output by
rapidly going back and forth from 1 to 0 logic. As you can see, the
simulation shows the circuit does exactly that.
Now
we will make the same circuit in a more concise manner. It is not
necessary to manually place 31 inverters in a row. Instead we can use
notation in the object properties of the inverter and the name of the
wires to achieve the exact same circuit. Following Tutorial 5, we name
our wires and inverter as shown below.
The
notation shown indicates that there are 31 inverters in series. We had
to press Q on the inverter and change the name to I0<1:31> in
order to indicate this, and name the input wires "osc_out,
out<1:30>"
to declare how the input wires feed into
each other from the first inverter on, then named the output wires
"out<1:30>,osc_out" to indicate that the output wires feed into
the next inverter and end at osc_out finally. This circuit is the same
as the first one and now it is time to make a layout.
Layout results:
Note
that if we LVS this extracted view, it will give an error, because we
do not have a designated output on the schematic. Therefore, we must
add one. Note that we had to add a thin wire with osc_out to the output
thick wire.
Now it will DRC/LVS just fine.
Now we have to make a symbol for the ring oscillator. First we have to delete the vdd section of the schematic.
Now we can make the schematic into a simple symbol and add a vdd and output wire to simulate it.
If you compare it to our first oscillator, the graphs are identical.
The
final part of the prelab is to simulate our extracted circuit, which we
do by altering the environment options in the ADE settings to use our
extracted view just as we did in previous labs.
As
you can see, our extracted layout functions identically to both of our
schematics, so the layout of a ring oscillator was a success. Thus,
prelab07 is concluded.
Main Lab Content:
Lab task 1:
4-bit word inverter design:
First
we are tasked with making a 4-bit word inverter using 6u/0.6u
transistors. This is four inverters in parallel, but we need to make it
a concise schematic like we learned to do in the prelab. Then we need
to attach the outputs to loads as specified:
- The out<0> is not connected to a load while out<3> is connected to a 100fF load.
- The out<1> is connected to a 1 pF load while out<2> is connected to a 500 fF load.
First, the schematic:
Then the symbol:
Finally, a circuit to simulate the symbol with the specified loads:
Simulation results:
You
can see from the simulation results that as the capacitive load
increases, we get more delay because the output has to spend more and
more time charging the capacitor. This circuit setup is good for
efficiently testing a design for different loads all at once.
Lab task 2:
Create schematics and symbols for an 8-bit input/output array of: NAND, NOR, AND, inverter, and OR gates.
Provide a few simulation examples using these gates.
First I will make each of the 8 bit symbols, then I will sim them all at once.
NAND:
Single NAND using 6u/0.6u transistors:
Single NAND symbol:
8bit schematic:
8bit NAND symbol:
NOR:
Single NOR using 6u/0.6u transistors:
Single NOR symbol:
8bit NOR schematic:
8bit NOR symbol:
AND:
Single AND using 6u/0.6u transistors:
Single AND symbol:
8bit AND schematic:
8bit AND Symbol:
INVERTER:
Single inverter using 6/0.6u transistors:
Single inverter symbol:
8bit Inverter schematic:
8bit Inverter symbol:
OR:
Single OR gate using 6u/0.6u transistors:
Single OR symbol:
8bit OR schematic:
8bit OR symbol:
Now
we need a circuit to simulate each of these designs. I decided to try
and simulate them all at once in one circuit using a similar load
layout to the 4-bit word inverter from earlier. The circuit is quite
large, but I only had to make one.
A closer look at the loads I used:
You
can see here that I just used 100fF, 200fF, 300fF, 400fF, 500fF, 1pF,
and 10pF capacitive loads as well as one bit completely free of load as
a control in order to test the designs. I used the same loads for each
gate.
SIMULATION RESULTS:
8bit AND:
You can see that the output is only high when both A and B are high. This is correct operation of an AND gate.
8bit inverter:
The inverter appears to correctly invert the input signal. You can see how the delay increases with capacitive load increase.
8bit NAND:
A NAND gate should output low only when A and B inputs are high. The simulation appears to show correct operation.
8bit NOR:
A NOR gate should only output high when both A and B are low. The simulation appears to show correct operation.
8bit OR:
An OR gate should be high when A, B or both are high. The simulation appears to show correct operation.
Judging
by the simulation results of each of these 8bit gates, it appears that
the designs were all successful and gave us a little insight into the
capacitive loads they can drive and the effects those loads have on the
outputs.
Lab task 3:
Simulate the operation of a 2-to-1 DEMUX/MUX using Spectre and explain how it works.
Make sure to show, using simulations, how the circuit can be used for both multiplexing and de-multiplexing.
Create an 8-bit wide word 2-to-1 DEMUX/MUX schematic and symbol.
Include
an inverter in your design so the cell only needs one select input, S
(the complement, Si, is generated using an inverter).
Use simulations to verify the operation of your design.
The
schematic for a 2-to-1 DEMUX/MUX using CMOS is shown below. MUX
operation works by using a selector bit 'S' to choose between one of
two input signals to allow through the device to the output. The
equation for MUX operation is Z = A*S + B*Si. DEMUX operation is the
reverse of this and takes a single input signal and outputs it at the A
or B terminal based on the selector bit. Since we expect this circuit
to DEMUX and MUX, we should make A. B, and Z into the input/output type
pins.
2-to-1 DEMUX/MUX symbol:
Simulations of DEMUX/MUX operation:
This
circuit allows us to simulate both MUX and DEMUX operations in one go.
Notice that an inverter is used to invert the S input to become Si, so
that we only need a single S signal for operation.
MUX Operation simulation:
You
can see here that the circuit follows the equation Z = A*S + B*Si. When
S is high, Si will be low due to the inverter, and will output whatever
signal A is. When S is low, Si will be high due to the inverter and
will output whatever signal B is.
DEMUX Operation simulation:
You
can see here that the input signal is now Z and whenever S is low, Si
will be high due to the inverter and it will output the Z signal to the
B output. When S is high, Si will be low due to the inverter and will
output the Z signal to the A output. This is the same process as MUX
operation, but in reverse.
Creating an 8-bit DEMUX/MUX:
Since
we know our DEMUX/MUX with the inverter for S works fine based on the
simulations, I decided to incorporate it into its own symbol before
making the 8-bit version.
Now
we have a compact, concise symbol that can be made into an n-bit
version easily. To do that we follow the same process as the other
gates earlier in the lab.
Now we have to test it, which I did using a similar method to testing the gates earlier with capacitive loads.
Testing MUX operation first:
You
can see from the graph that the 8bit MUX still follows the equation Z =
A*S + B*Si, but has 8 parallel outputs that we can attach different
loads to in order to test how the circuit handles different loads. Next
we can test the DEMUX operation, which I did in the same way, but using
the same settings that I tested the single DEMUX with for consistency.
I also added capacitive loads to the outputs of this circuit, which
caused the graph to be a little congested, but the results were overall
the same as the original.
Testing DEMUX operation:
The
8-bit DEMUX works the same as the single DEMUX and outputs to A when S
is high, but outputs to B when S is low. This is the correct operation
of the circuit and you can see the effects different capacitive loads
have on the output as well. Overall, it appears that construction of
the 8-bit DEMUX/MUX was a success!
Lab task 4:
Draft the schematic of the full-adder seen in Fig. 12.20 using 6u/0.6u devices (both PMOS and NMOS).Create an adder symbol for this circuit (see the symbol used in lab6).
Use this symbol to draft an 8-bit adder schematic and symbol.
For
how to label the bus so the carry out of one full-adder goes to the
carry in of another full-adder review the ring oscillator schematic
discussed in Cadence Tutorial 5.
Simulate the operation of your 8-bit adder.
Lay out this 8-bit adder cell (*note* that this is the only layout required in this lab).
Show that your layout DRCs and LVSs correctly.
Using
the AOI implementation of a 1-bit full adder seen in figure 12.20 of
our textbook, I generated the following schematic. I used my own
inverter from a previous lab, as well as wire labels to make
connections clean and concise.
Using
this schematic and symbol, we are able to draft a schematic for an 8bit
version of the full adder, but it is a little more complicated due to
the fact that we need the Cout of one adder to go to the Cin of the
next. The schematic that I came up with is shown below. It utilizes the
techniques we learned in Tutorial 5 as well as what we learned during
this lab so far. Notice that the inputs utilize both parallel and
serial techniques. We need both because, while the full adders are in
parallel, their Couts to Cins are in series.
Testing the 8-bit Full Adder:
To
test the 8-bit full adder, I used static DC inputs on each input bit in
order to manually input 8-bit entries to be added together.
Here I input A = 0100110 (77) and B = 00001110 (14), which should equal S = 001011011 (91) with the carry out bit.
Simulating the circuit we get the results:
The
results shown are S = 001011011 (91) just like we expected. This shows
that our circuit is able to add correctly, but we should make sure that
our carry out bit is working properly by adding bigger numbers.
I
reran the simulation using A = 11111111 (255) and B = 11111111
(255). These are the biggest numbers we can add and should add up to S
= 111111110 (510), with the carry bit being our 9th bit equal to 1.
As
you can see, S = 111111110 (510) just like we expected. Thus, we can
conclude that the simulation of our 8-bit adder circuit is working
correctly.
Next we need to layout our Full Adder circuit.
Layout of Full Adder circuit:
First, I laid out the single full adder in order to use it to instantiate them in the 8-bit version to save time and effort.
The
single full adder LVS and DRC'd just fine. Next, I laid them out next
to each other and connected their Cout terminals to the next one's Cin
terminal, except the first Cin and the last Cout<7>. Each of the
A, B, and S terminals had to correspond to their respective number in
the array <7:0> in order to LVS properly, but only Cin and
Cout<7> needed to be pins on the design because they were output
pins on the schematic.
Click each image to open in a new window and zoom in (they are very large).
You can see that the layout and extracted layout LVS and DRC without any issues, so our work is complete.
Backing up our work:
As
always we must back up our work. I back up my work by downloading the
working directory, zipping it up, and uploading it to my Google Drive.
With
our 8-bit gates, 8bit DEMUX/MUX, and 8bit Full Adder designed,
simulated and laid out (full adder only), Lab 7 is concluded.
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