Lab 8 - EE 421L Digital Integrated Circuit Design, Fall 2020
Author: William Wherry
Email: wherrw1@unlv.nevada.edu12/2/2020
Generating a test chip layout for submission to MOSIS for fabrication
Pre-lab work
- Back-up all of your work from the lab and the course.
- Go through Cadence Tutorial 6 seen here.
- Read through the lab in its entirety before starting to work on it
For this laboratory, we will be creating a padframe using pads laid out in the C5 process. Following the instructions in Tutorial 6 we lay out a single pad to be used in a larger padframe layout later.
The schematic is very simple since it is only a pin. The symbol is also very straightforward.
Next,
we have to place 40 pads in a schematic that will be the standard for
laying out chips to be fabricated. Following the instructions in
Tutorial 6 we get the following layout.
The
chip size must be smaller than 1.5mm for the process we are using and
this layout measures 1.395mm, so we are good. The extracted layout is
seen below.
Next we have to make a concise schematic and symbol to be used to connect all devices we want in our chip in a schematic view.
Now
we are ready to design a chip that can be fabricated, so we make a new
schematic view and follow the instructions on Tutorial 6 to name all of
the wires corresponding to each pin we want them attached to in the
layout. We are just going to use some of the designs we created in
earlier tutorials.
Notice
here that we are using pin 20 as a common ground for all of the devices
and pin 40 as a common VDD for all of the devices that use it. All
other pins correspond to a pad in the layout we make, which is seen
below.
A zoom in example of the connections to the oscillator connected to pad<1> is seen below.
The extracted layout and DRC/LVS results:
BACKING UP OUR WORK:
As
always, we must backup our work. I back up my work by downloading the
directory, zipping it up, and saving it in my Google Drive.
With our padframe (which we can reuse in the main lab) and example chip laid out and DRC/LVS'd, prelab 8 is concluded.
Main Lab Content:
Form into groups of 3 students that will put the test structures on the chip.
Each test circuit should have its own power but ground should be shared between the circuits.
Ground should be pin 20.
Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable.
The image
seen at the bottom of the page shows how the chip's pads correspond to
the pins of the 40 pin DIP package we'll receive from MOSIS.
Your chip should include the following test structures:
- One, or more if possible, course projects
- A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
- NAND and NOR gates using 6/0.6 NMOSs and PMOSs
- An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
- Transistors,
both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each
device are connected to bond pads (7 pads + common gnd pad)
- Note
that only one pad is needed for the common gnd pad. This pad is used to
ground the p-substrate and provide ground to each test circuit
- Using
the 25k resistor laid out below and a 10k resistor implement a voltage
divider (need only 1 more pad above the ones used for the 25k
resistor)
- A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)
- Whatever else you would like to fabricate to use the remaining pins on the chip
- Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Copy the final, DRC and LVS clean cell you want to fabricate, and then add the graphic since the graphic won't DRC
- Also
note that you can reduce the number of pins needed by sharing some
of them (two resistors, for example, only need 3 pins)
In your CMOSedu.com lab account create a directory called lab8.
Create a Cadence design directory called ChipX_f18 where X is the number the lab instructor will assign after the groups are formed.
Put the details of your chip (how to test it) in your lab report in this directory. *Be simple and clear.*
Schematics with pin numbers and SIMPLE directions on how to test the chips should be the main content of these reports.
If your group's chip is fabricated it will be tested the next time the lab is taught.
MOSIS
returns 5 packaged chips for each design submitted for
fabrication so it's possible that each member of a group, as long
as they test the chip and report on how it worked, can get a chip
to keep.
Your report should include a link to your zipped up design directory for future reference.
This design directory should
be "clean" meaning that it only contains the cells (schematics,
symbols, layouts, and simulations) used in the final chip.
The
top level cell, the one that will be fabricated, should be called
ChipX_f18 and have both schematic and layout views so that it can
be DRCed, and LVSed.
Please
note that due to different circumstances, my group split up and I am
doing this lab on my own with Professor Baker's approval.
The
first thing I did was plan out my chip. I printed out a picture of the
padframe designed in the prelab and drew how I wanted to lay out my
devices on the chip. We were not supposed to use shared power supplies,
so each device had to have its own "VDD." Because of this fact, I had
to redesign every single schematic that did not have a VDD input pin to
have one, including my final lab project. First, I will show every
device that was placed on the chip individually, then I will show them
placed on the chip with a table of corresponding pins.
Devices on the chip:
1) Final Project, details of which can be found here in the lab report.
Schematic & symbol:
Layout & Extracted:
2) 6u/0.6u PMOS:
Schematic & Symbol:
Layout & Extracted:
3) 6u/0.6u NMOS:
Schematic & Symbol:
Layout & Extracted:
4) Voltage Divider using a 25k and 10k resistor:
Schematic & Symbol:
Layout & Extracted:
5) 25k Resistor alone:
Schematic & Symbol:
Layout:
6) NAND Gate using 6u/0.6u devices:
Schematic & Symbol:
Layout & Extracted:
7) NOR Gate using 6u/0.6u devices:
Schematic & Symbol:
Layout & Extracted:
8) inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS:
Schematic & Symbol:
Layout & Extracted:
9) 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load:
31-stage oscillator schematic & symbol:
31-stage oscillator layout & extracted:
Buffer schematic & symbol:
Buffer layout & extracted:
Combined Oscillator & Buffer Schematic & Symbol:
Combined Oscillator and Buffer layout & extracted:
Those
were all of the required devices, which were mostly devices already
made before in class and lab which needed to be modified slightly. Now
I will go over the devices I chose to add to take up the remaining pads.
11) 2-input XOR gate:
Schematic & Symbol:
Layout & Extracted:
12) 2-input AND Gate:
Schematic & Symbol:
Layout & Extracted:
13) 2-input OR gate:
Schematic & Symbol:
Layout & Extracted:
Placing the devices on the chip
Next,
it is time to place all the devices on the chip. I used the exact same
procedure as Tutorial 6, except now there is no VDD pin. Following the
plan that I laid out on paper, the final design is shown below.
Schematic:
Layout (click for larger image):
Extracted (click for larger image):
DRC & LVS:
The
design DRC's and LVS's just fine, so it appears that the chip design
was a success. Next I will talk about the pin layout and how to use the
chip.
Pin table
| Pin | Device | Purpose |
| 40 | 2-input OR Gate | Input A |
| 1 | 2-input OR Gate | Input B |
| 2 | 2-input OR Gate | Power In |
| 3 | 2-input OR Gate | Output |
| | |
| 4 | 25K Resistor | Input |
| | |
| 5 | 31-stage Oscillator with Buffer capable of driving 20pF | Output |
| 6 | 31-stage Oscillator with Buffer capable of driving 20pF | Power In |
| | |
| 7 | Inverter with 6u/0.6u NMOS and 12u/0.6u PMOS | Inverted Output |
| 8 | Inverter with 6u/0.6u NMOS and 12u/0.6u PMOS | Power In |
| 9 | Inverter with 6u/0.6u NMOS and 12u/0.6u PMOS | Input |
| | |
| 10 | 2-input NOR Gate | Output |
| 11 | 2-input NOR Gate | Power In |
| 12 | 2-input NOR Gate | Input A |
| 13 | 2-input NOR Gate | Input B |
| | |
| 14 | 2-input NAND Gate | Output |
| 15 | 2-input NAND Gate | Power In |
| 16 | 2-input NAND Gate | Input A |
| 17 | 2-input NAND Gate | Input B |
| | |
| 18 | Final Project: Digital Receiver | Input D (not inverted) |
| 19 | Final Project: Digital Receiver | Input Di (inverted) |
| 20 | Common Ground | Common Ground |
| 21 | Final Project: Digital Receiver | Power In |
| 22 | Final Project: Digital Receiver | Output |
| | |
| 23 | 6u/0.6u PMOS | Source |
| 24 | 6u/0.6u PMOS | Gate |
| 25 | 6u/0.6u PMOS | Drain |
| 26 | 6u/0.6u PMOS | Body |
| | |
| 27 | 6u/0.6u NMOS | Drain |
| 28 | 6u/0.6u NMOS | Gate |
| 29 | 6u/0.6u NMOS | Source |
| | |
| 30 | 25k/10k Resistors Voltage Divider | Input |
| 31 | 25k/10k Resistors Voltage Divider | Output |
| | |
| 32 | 2-input XOR Gate | Input A |
| 33 | 2-input XOR Gate | Input B |
| 34 | 2-input XOR Gate | Power In |
| 35 | 2-input XOR Gate | Output |
| | |
| 36 | 2-input AND Gate | Input A |
| 37 | 2-input AND Gate | Input B |
| 38 | 2-input AND Gate | Power In |
| 39 | 2-input AND Gate | Output |
Assuming
this chip is fabricated, you would utilize it like any other packaged
chip. I am most familiar with simply using them on a breadboard with
jumper cables, following pin tables just like the one above. Power is
provided to the Power In pin of whichever device is needed using a
power supply like any you would find in a lab. Ground is common to all
of the devices, so you would simply connect that pin to your ground.
After that you can use the inputs and outputs as you see fit like any
other chip.
Since
the layout was successful and the pin table laid out plain and simply,
it is time to back up our work and prepare the design directory in case
it is ever fabricated.
Zipped up chip directory:
Chip4_f20.zip
Backing up our work:
As always we must back up our work. I do this by uploading the zipped directory to Google Drive.
With the chip designed, laid out, backed up, and ready for fabrication, Lab 8 is concluded.
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