EE 421L Digital Integrated Circuit Design Laboratory
Fall 2015, University
of Nevada, Las
Student lab reports
are found here.
grades are located here.
Project – your end of semester projects will be fabricated using the C5 process through MOSIS. These chips will be used next time EE 421L is
taught to add an electrical measurement component to the lab.
projects fabricated as a result of this lab are:
, top3, top4, top6, and top7
half of the project (no layout, just schematics and symbols), of
your design and an html report detailing operation (including
simulations), is due at the beginning of lab on Nov. 9.
Ensure that you have schematics with simulations for all of the cells listed below.
up/down counter, for example, should be simulated showing,
counting up, down, or both, resetting then counting, etc.
Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu.
Dr. Baker will go over your designs with you, including running simulations, when lab meets on Nov. 9.
Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 23.
I will meet with you on Nov. 23 to go over your layout and, again, put
your report in the /proj folder in your directory at CMOSedu.
Ensure that there is a link on your project report webpage to your zipped design directory.
Finishing the projects by Nov. 23 will give us time to assemble chips for fabrication through MOSIS.
- Design of an 8–bit resettable (input "clear") up/down counter
- The outputs of your counter should be buffered before connecting to a pad
- A 31–stage ring oscillator with a buffer for driving a 20 pF off–chip load
- NAND and NOR gates using 6/0.6 NMOSs and PMOSs
- An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each
device are connected to bond pads (7 pads + common gnd pad)
that only one pad is need for the common gnd pad. This pad is used to
ground the p–substrate and provide ground to each test circuit
the 25k resistor laid out below and a 10k resistor implement a voltage
divider (need only 1 more pad above the ones used for the 25k
- A 25k resistor implemented using the n–well (connect between 2 pads but we also need a common gnd pad)
November 23 – Lab8 – Generating a test chip layout for submission to MOSIS for fabrication, due November 30
October 19 – Lab7 – Using buses and arrays in the design of word inverters, muxes, and high–speed adders, due November 2
October 5 – Lab6 – Design, layout, and simulation of a CMOS NAND gate, XOR gate, and Full–Adder, due October 19
September 28 – Lab5 – Design, layout, and simulation of a CMOS inverter, due October 5
September 21 – Lab4 – IV characteristics and layout of NMOS and PMOS devices in ON's C5 process, due September 28
September 14 – Lab3 – Layout of a 10–bit DAC, due September 21
September 7 – Labor day recess
August 31 – Lab2 – Design of a 10–bit digital–to–analog converter (DAC), due September 14
August 24 – Lab1 – Laboratory introduction, generating/posting html lab reports, installing and using Cadence, due August 31
Instructor: R. Jacob Baker
Lab Assistant: Yiyan Li
Time: Monday from 8:30 to 11:15 AM
dates: Monday, August 24
to Monday, November 30
Location: TBE B–350
Holidays: Monday, September 7
(Labor Day Recess)
Course content – Laboratory
based analysis and design of digital and computer electronic systems.
Corequisite: EE 421;
Prerequisite: EE 320L
40% Lab Reports
the lectures, laptops can be used during the lab. Please bring your laptop with you
a quiz is open book then only the course textbook can be used (no
Kindle, Nook, etc., older/international editions, or photocopies).
late work accepted. Regularly
being tardy for labs, leaving in the middle of labs, or leaving early
is unacceptable without consent of the instructor.
or plagiarism will result in an automatic F grade in the lab
for the instructor (only) should be asked in person (not via email).