Final Project - ECE 421L 

Chip6_F15

Giang Tran - trang@unlv.nevada.edu

Gerardo Gomez-Martinez - gomezmar@unlv.nevada.edu

Emmanuel Sanchez - sanch512@unlv.nevada.edu

Jesse Horsman - horsman@unlv.nevada.edu

11/26/2015

Lab description:

• One up/down counter with clear
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)

NOTE: Each test circuit should have its own power but ground should be shared between the circuits!
              Pad(20) serves as a common ground to all test structure!!!!

Chip structure

The configuration of padframe follows the bonding diagram below. All the pins are labeled accordingly.



Full Chip Layout



Pin Assignment
We'll follow the bonding diagram up above to assign specific pad numbers to our structure pins.
All pad numbers are labeled from 1 to 40 (unless not used!).


S<0-7> are our input, and C<0-7> are outputs







Structure Connections and Testing
Voltage Divider

To measure the resistance of the 25K Ohms resistor,  we probe pad(14) and pad(15).
    To measure the output voltage of the voltage divider, we'll apply a known voltage to pad(16) and probe pad(15) using a multimeter to get the appropriate output voltage.

NMOS

    Connect Drain to a fixed 5V power supply; pad(12).
    Connect Source to GND; pad(11).
    Connect Gate to an adjustable power supply; pad(13).
    Increase the Gate voltage until current flows from Drain to Source. NMOS turns on when V(gate) is greater than V(threshold).

PMOS

    Apply a fixed 5V voltage to Source terminal; pad(9).
    Connect Drain to GND; pad(7).
    Connect Base to a fixed 5V voltage; pad(8).
    Connect Gate to an adjustable power supply; pad(10).
    When Gate is at 5V there's no current flowing from Source to Drain terminals. As the voltage from Gate is decrease below 5V - V(threshold), you'll get some current flowing and increases as Gate voltage drops.

NAND/NOR/INVERTER

Ring Oscillator

    Connect power to pad(17) to power up our ring oscillator. We'll then use an oscilloscope probe to determine the oscillation frequency and time delay through pad(14).

Counter

    Our counter has 21 inputs with Load which is fully programmable. That is, the input can be preset to any value desired. When Load is high the data from our input pins are loaded into the counter.
    Connect pad(18) to 5V to power up the counter.

DRC and LVS Check
Before we conclude our Final Lab for submission. Let's make sure everything work properly!
DRC check

LVS Check

Saving My Work!!!

All files and images are backed up in a folder on my desktop,

I'll then send a copy to my email as a backup. 

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