Lab #8: MOSIS_chip4 

Authored by:

Brian Kieatiwong, kieatiwo@unlv.nevada.edu

Cassandra Williams, willi131@unlv.nevada.edu

Mari Gilligan  mgill19@unlv.nevada.edu

Russ Prado, prador@unlv.nevada.edu

11/29/2015

  

Generating a Test Chip Layout for submission to MOSIS for Fabrication

Pre-lab work:

_____________________________________________________________________________________

Lab Report:

In this lab we are putting together a test chip that will be submitted for MOSIS fabrication.

The following structures will be included within this test chip:

MOSIS_Chip4 Test Instructions:

The simulations for each of these devices can be found at Lab Project

MOSIS_Chip4 Padframe:




lab8.zip


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