Lab 8: Generating a Test Chip Layout for Submission to MOSIS for Fabrication - EE 421L     

Authored By:

    Jonathan DeBoy

    Steven Leung

    Matthew Meza

    Joey Yurgelon

November 24th, 2015

yurgelon@unlv.nevada.edu

• Students will lay out a set of test structures on a chip for manufacture.

Your chip should include the following test structures:

• One up/down counter with clear
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)   
• Whatever else you would like to fabricate to use the remaining pins on the chip
• Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Copy the final, DRC and LVS clean cell you want to fabricate, and then add the graphic since the graphic won't DRC
• Also note that you can reduce the number of pins needed by sharing some of them (two resistors, for example, only need 3 pins)

• ALL OF THE DESIGN FILES ASSOCIATED WITH THIS LAB CAN BE FOUND HERE.

Experimental Results: 

• In out set of test structures, our counter also is equipped with a synchronous load, enable line, and set line. By this notion, we had a difficult time deciding which pins we would need to eliminate so that all of our structures were equally represented in the 40 pin frame. Extra pins would also need to be dedicated to powering up separate test structures to eliminate the chance of shorting all of the devices simulataneously. This effort can be noted below with the drawn schematic of of our chip layout. This should make it clear as to which device corresponds to which pin, and give the user an easy schematic to follow once testing. Note that there are separate supply voltages on-chip. This allows the user to power the desired circuitry without risking a short through all the devices (VDD1 is used to power all of the circuitry related to the counter, VDD2 takes care of the ring oscillator, and VDD3 powers the logic as well as the NMOS/PMOS).
• We made use of both the analog and digital pads given to us so that all inputs, and outputs were buffered. This ensures that getting signals off chip, and on chip will take minimal effort for the user whom should not have to worry about an input signal being slightly non-ideal. 

Fig. 1 - Padframe Circuit Layout

Fig. 2 - Chip Schematic

Fig. 3 - Chip DRC Clean

Fig. 4 - Chip LVS Clean

• NOTE: Any time a separate VDD must be used (i.e VDD1, VDD2, VDD3), pin 40 must be connected, and a jumper wire must bridge pin 40 and the respective power. For example, to power the logic gates, pin 40 must be connected to a source, and a jumper wire must connect pin 40 to pin 7. This ensures that the ESD protection is properly powered, and operational.

• As seen above, the resistor divider is attached between pins 4 and 3 of the chip. To make sure that the PN junction between the N-Well of the resistors, and the P-Substrate of the bulk is reverse biased, apply ground to pin 20. From here, the divider should function as intended. 
• Mesuring the 25kOhm resistor:
• Connect pin 20 to ground. 
• Using a multimeter, place one lead on pin 3 and the other on pin 4.
• Record the result.
• Measuring the 10kOhm resistor: 
• Connect pin 20 to ground.
• Using a multimeter, place one lead on pin 3 and the other on pin 20.
• Record the result. 
• Voltage Divider:
• Connect pin 20 to ground. 
• Using a DC power supply, connect +5V to pin 4. 
• Connect a jumper from pin 4 to pin 40.
• Using a multimeter, place one lead on pin 4 and the other on pin 20.
• With the notion of a voltage divider, we should see around +1.428 V at on pin 4. 
• Record the result. 

• As seen above, the oscillator is powered by pin 6 with an output on pin 5. The oscillator will break away to the counter, but this will be discussed elsewhere. To be able to measure the ring oscillator, a buffer has been added internally in the chip. This buffer should be enough to drive the ~20 pF capacitance of the scope probe. By setting the attenuation of the scope probe and the oscilloscope to x10, we can reduce that capacitance slightly for better performance. In every instance, we must connect pin 20 to ground, and pin 6 to vdd. Note that with a oscillator frequency of 150 MHz , the bandwidth of the oscilloscope begins to play a role in the accuracy of the measurement.
• Mesuring the Ring Oscillator Frequency:
• Connect pin 20 to ground. 
• Connect pin 6 to vdd.
• Connect a jumper from pin 6 to pin 40
• Using a scope probe (x10 attenuation), connect to the output of the ring oscillator on pin 5. 
• After obtaining a few cycles of the oscillator on ones oscilloscope, measure the time it takes for a full period to occur. 
• Find the measured frequency of the device by the following formula: F = 1/T where T is the time for a single period. 
• Record the result.  

• To test the Logic gates on the chip we must utilize pads 9,10,11,12, and pin 20.
• Beware of ESD, as it will blow up the chip. Literally. The chip will explode and there will be mini shrapnel everywhere.
• Supply the power to the logic gates.
• Power goes to pin 7 and ground goes to pin 20.
• Connect a jumper from pin 7 to pin 40.
• The inputs of all three logic gates (NAND, NOR, Inverter) are all tied together.
• Input A is pin 8, and Input B is pin 9. The output of the inverter is pin 10. The output of the NAND gate is pin 11. The output of the NOR gate is pin 12.
• Users should input DC voltages into the inputs A and B.
•  If a clock is used as an input, make sure that its frequency is less than 100 Hz.
• The Logic Gates are NOT designed to drive the large capacitance of the scope-probe.  

• Connect power to pin 40.
• In most discrete chips, the body of the MOSFET is tied to its source terminal! 
• With this chip, the body of the PMOS is tied to it's respective source terminal to minimize body effect.
• The body of the NMOS is tied to ground. This means that the NMOS transistor will NOT operate properly unless the global ground (pin 20) is connected to ground. 
• If the source of the NMOS is tied to ground, the body effect will be minimized. The source however does NOT have to be tied to ground. 
• If the source is not tied to ground, the transistor will have body effect.
• Beware of ESD, as it will blow up the chip. Literally. The chip will explode and there will be mini shrapnel everywhere.
• Testing the NMOS and PMOS:
• First create a circuit (on paper) to test the characteristic curves of the NMOS and PMOS transistor. 
• If you do not know how you can find it in the CMOS book. 
• After you have the circuits on paper, implement it using the chip.
• The drain of the NMOS is connected to pin 16.
• The source (and body) of the NMOS is connected to pin 18.
• The gate of the NMOS is connected to pin 17.
• The drain of the PMOS is connected to pin 15.
• The gate of the NMOS is connected to pin 14.
• The source of the NMOS is connected to pin 13.

• If one wishes to use the internal oscillator, power must be supplied to pin 6 via a jumper from pin 40.
• Our up down counter has the following functionality: up/down count, parallel load, clear, and the option for an external clock. Pins 32-39 are the outputs, pins 22-29 are the load inputs, up/down is on pin 19, load is on pin 21, enable is on pin 2, clear is on pin 1, the external clock goes on pin 30 and clock select is on pin 31. Note that VDD for the counter is pin 40 (global VDD).
• Up/down counting
• The enable and clear pin has to be a logic high for the counter to count up or down. A logic “0” on the up/down pin will make the counter count up while a logic “1” will make the counter count down. We have a asynchronous clear meaning that whenever the clear pin goes low, regardless of the clock edge, the output of the counter will go to zero. Whenever the enable pin is a logic low, the counter will not count.
• Loading
• A logic “1” on the load pin will load in the values at the load pins on the next rising edge of the clock.
• Using an external clock
• Our counter has the option to use the on board oscillator as the clock driving the counter and the option to use an external off chip clock. A logic “0” at the clock select pin will result in the counter using the on chip oscillator as a clock (150 Mhz). If the clock select pin is a logic “1”, the user can apply an external clock on the external clock pin to drive the counter.

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