Lab 8: Generating a Test Chip Layout for Submission to MOSIS for Fabrication - EE 421L     

Authored By:

    Jonathan DeBoy

    Steven Leung

    Matthew Meza

    Joey Yurgelon

November 24th, 2015

Lab Description:
Lab Requirements:

Your chip should include the following test structures:



Experimental Results: 

Fig. 1 - Padframe Circuit Layout

Fig. 2 - Chip Schematic

Fig. 3 - Chip DRC Clean

Fig. 4 - Chip LVS Clean

Test Manual:
    Resistor/Divider:     Ring Oscillator:     Logic Gates:      NMOS/PMOS:
    8-bit Up/Down Counter:



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