EE 421L Digital Integrated Circuit Design - Lab 8

Generating a test chip layout for submission to MOSIS for fabrication

Pre-lab work

• Back-up all of your work from the lab and the course.
• Go through Cadence Tutorial 6 seen here.
• Read through the lab in its entirety before starting to work on it

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Form into groups of 4 students that will put the test structures on the chip.
Each test circuit should have its own power but ground should be shared between the circuits.
Power should not be shared between the circuits so that a vdd!-gnd! short in one circuit doesn't make one of the other circuits inoperable.

The image seen at the bottom of the page shows how the chip's pads correspond to the pins of the 40 pin DIP package we'll receive from MOSIS. 

Your chip should include the following test structures:

• One up/down counter with clear
• The outputs of your counter should be buffered before connecting to a pad
• A 31-stage ring oscillator with a buffer for driving a 20 pF off-chip load
• NAND and NOR gates using 6/0.6 NMOSs and PMOSs
• An inverter made with a 6/0.6 NMOS and a 12/0.6 PMOS
• Transistors, both PMOS and NMOS, measuring 6u/0.6u where all 4 terminals of each device are connected to bond pads (7 pads + common gnd pad) 
• Note that only one pad is need for the common gnd pad. This pad is used to ground the p-substrate and provide ground to each test circuit
• Using the 25k resistor laid out below and a 10k resistor implement a voltage divider (need only 1 more pad above the ones used for the 25k resistor) 
• A 25k resistor implemented using the n-well (connect between 2 pads but we also need a common gnd pad)   
• Whatever else you would like to fabricate to use the remaining pins on the chip
• Feel free to "sign" the chip or add a graphic (see the bottom of this webpage). Copy the final, DRC and LVS clean cell you want to fabricate, and then add the graphic since the graphic won't DRC
• Also note that you can reduce the number of pins needed by sharing some of them (two resistors, for example, only need 3 pins)

In your CMOSedu.com lab account create a directory called lab8.

Create a Cadence design directory called MOSIS_chipX where X is a number the lab instructor will assign after the groups are formed.
Put the details of your chip (how to test it) in your lab report in this directory.
Schematics with pin numbers and SIMPLE directions on how to test the chips should be the main content of these reports.
If your group's chip is fabricated it will be tested the next time the lab is taught.
MOSIS returns 5 packaged chips for each design submitted for fabrication so it's possible that each member of a group, as long as they test the chip and report on how it worked, can get a chip to keep.

Your report should include a link to your zipped up design directory for future reference.
This design directory should be "clean" meaning that it only contains the cells (schematics, symbols, layouts, and simulations) used in the final chip.

The top level cell, the one that will be fabricated, should be called topX and have both schematic and layout views so that it can be DRCed, and LVSed.

Each student must have a lab8 html lab report in their lab8 directory at CMOSedu.com; however, feel free to copy from each other.
If you use the same html report that is okay as long as all students names are listed on it and all students contributed to the design of the chip.



Again, ensure that your html lab report includes your name, and the names of the other students in your group along with your email
addresses at the beginning of the report (the top of the webpage).

When finished backup your work (webpages and design directory).