EE 421L Digital Electronics Lab
Fall 2013, University of Nevada, Las Vegas

 

Student lab reports are found here.

 

Current grades are located here.

 

Project - design, layout, and simulate an 8-bit ALU that can perform: A AND B, A OR B, A + B (addition), and A - B (subtraction).

First half of the project (no layout), a jelib of your design and an html report detailing operation (including simulations), is due at the beginning of lab on Nov. 8

The top level ALU icon used for simulations should have the following inputs (all bus connections): A (8-bits), B (8-bits),  F (2 bits), and Z (8-bits).

Ensure that you have input vectors saved for simulations when I run IRSIM (make it easy for me to verify your design works).

Put your report (proj.htm) in a folder called /proj in your directory at CMOSedu

I will go over your designs with you, including running simulations, when we meet on Nov. 8.

Second half of the project, a verified layout and documention (in html), is due at the beginning of lab on Nov. 22.

Again, I will meet with you on Nov. 22 to go over your layout and, again, put your work in the /proj folder in your directory at CMOSedu

Finishing the projects by Nov. 22 will give us time to assemble chips for fabrication through MOSIS.

 

December 6 - Lab8 - Generating a test chip layout for submission to MOSIS for fabrication 

November 1 - Lab7 - Using buses and arrays in the design of word inverters, muxes, and high-speed adders  

October 11 - Lab6 - Design, layout, and simulation of CMOS NAND/NOR/XOR gates and a full-adder 

October 4 - Lab5 - Design, layout, and simulation of a CMOS inverter   

September 27 - Lab4 IV characteristics of NMOS and PMOS devices in ON's C5 process  

September 20 - Lab3 - Layout of a 10-bit digital-to-analog converter (DAC)

September 6 - Lab2 - Design of a 10-bit digital-to-analog converter (DAC)  

August 30 - Lab1 - Laboratory introduction, generating/posting html lab reports, installing and using Electric 

  

Instructor: R. Jacob Baker

Lab Assistant: Stephen Wu
Time: Friday from 11:30 AM to 2:15 PM

Course dates: Friday, August 30 to Friday, December 6

Location: TBE B-350

Holidays: Friday, October 25 (Nevada Day Recess) and Friday, November 29 (Thanksgiving Recess)

Course content Laboratory based analysis and design of digital and computer electronic systems.

Credits: 1

Corequisite: EE 421; Prerequisite: EE 320L

 

Grading
30% Quizzes
40% Lab Reports

30% Project
 

Policies 

  • Unlike the lectures, laptops can be used during the lab. Please bring your laptop with you to lab!
  • If a quiz is open book then only the course textbook can be used (no ebooks, Kindle, Nook, etc., older/international editions, or photocopies).
  • No late work accepted. Regularly being tardy for labs, leaving in the middle of labs, or leaving early is unacceptable without consent of the instructor.
  • Cheating or plagiarism will result in an automatic F grade in the lab
  • Questions for the instructor (only) should be asked in person (not via email).
  

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