EE 421L Digital Integrated Circuit Design - Lab 2

Design of a 10-bit digital-to-analog converter (DAC) 

Pre-lab work

• Back-up all of your work from the lab and the course.
• Download the lab2.jelib which contains a simulation example using an ideal 10-bit Analog-to-Digital Converter (ADC) and 10-bit DAC.
• Open, using Electric, your lab/course jelib (below this is ee421_ecg621.jelib) and the lab2.jelib you just downloaded
• Use the Electric menu command Cell -> Cross-Library Copy...
• The cell sim_ADC_DAC{sch} contains the ideal 10-bit ADC and DAC. 
• Copy sim_ADC_DAC{sch}, all of its subcells, and all related views into your lab/course jelib

• When finished hit "Done" and then close the lab2.jelib in Electric's Explorer so that only the course/lab jelib is open as seen below
• Next Save your course/lab jelib (circled floppy disk seen below)
• Your course/lab jelib should now also contain the copied cells related to the ideal 10-bit ADC and DAC
• Backup this library

• Run the simulation setup in the cell sim_ADC_DAC seen above to get the following

• Prior to coming to lab make sure you understand how the input voltage, Vin, is related to B[9:0] and Vout
• In your lab report: 1) provide narrative of the steps seen above, 2) provide, and discuss, simulation results different from the above to illustrate your understanding of the ADC and DAC, 3) explain how you determine the least significant bit (LSB, the minumum voltage change on the ADC's input to see a change in the digital code B[9:0]) of the converter. Use simulations to support your understanding.
• Backup your webpages and design diretory.

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In this lab we'll use n-well resistors to implement a 10-bit DAC.
Our design is based upon the topology seen in Fig. 30.14, below, in the CMOS book.
The controlling input bits seen below come from the ADC.



Your lab report should document the following:

• The design of a 10-bit DAC using an n-well R of 10k
• The 2R resistor should be implement with two separate 10k resistors in series
• After you've designed and drafted your schematic check it using Tools -> DRC -> Check Hierarchically or just hit F5
• The most common error, when drafting schematics, is extra pins (remove extra pins using Edit -> Cleanup Cell -> Cleanup Pins Everywhere)
• How to determine the output resistance of the DAC (answer: R) by combining resistors in parallel and series
• Delay, driving a load
• Ground all DAC inputs except B9. Connect B9 to a pulse source (0 to VDD) and show, and predict using 0.7RC, the delay the DAC has driving a 10 pF load
• Verify the simulation results match your hand calculations
• How to create an icon for your design with the exact same footprint as the 10Bit_Ideal_DAC 
• See tutorials for help with off-page connections and exports
• Simulations to verify your design functions correctly.
• Copy the cell sim_ADC_DAC{sch} to a cell sim2_ADC_DAC{sch} and replace the ideal DAC with the one you just designed
• Use the sim2_ADC_DAC{sch} to illustrate that your design works as expected. 
• Show what happens if the DAC you designed drives a load (both R, C, and R/C)
• Explain what happens if the DAC drives a 10k load?
• In a real circuit the swithces seen above (the outputs of the ADC) are implemented with transistors (MOSFETs). 
• Discuss what happens if the resistance of the switches isn't small compared to R.

Ensure that your html lab report includes your name and email address at the beginning of the report (the top of the webpage).
When finished backup your work (webpages and design directory).